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may 2009 doc id 7838 rev 2 1/104 1 psd4135g2 psd4135g2v flash in-system programmable peripherals for 16-bit mcus features single supply volate ? 3 v10% (psd4135g2v) ? 5 v10% (psd4135g2) up to 4 mbit of primary flash memory (8 uniform sectors) 256 kbit secondary flash memory (4 uniform sectors) up to 64 kbit sram over 3,000 gates of pld: dpld and cpld 52 reconfigurable i/o ports enhanced jtag serial port programmable power management high endurance: ? 100,000 erase/write cycles of flash memory ? 1,000 erase/write cycles of pld www.st.com obsolete product(s) - obsolete product(s)
contents psd4135g2, psd4135g2v 2/104 doc id 7838 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 in-system programming (isp) via jtag . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1.1 first time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1.2 inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 10 1.1.3 expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 in-application programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.1 simultaneous read and write to flash memory . . . . . . . . . . . . . . . . . . . 10 1.2.2 complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.3 separate program and data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.4 psdsoft? express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 psd architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 plds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 mcu bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 isp via jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 in-system programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 in-application programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 psd register description and address offsets . . . . . . . . . . . . . . . . . . . 23 6 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 data-in registers - port a, b, c, d, e, f, g . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 data-out registers - port a, b, c, d, e, f, g . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 direction registers - ports a, b, c, d, e, f, g . . . . . . . . . . . . . . . . . . . . . . 24 6.4 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v contents doc id 7838 rev 2 3/104 6.5 drive registers - ports a, b, d, e, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.6 drive registers - ports c and f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7 flash memory protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.8 flash boot protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.9 page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.10 pmmr0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.11 pmmr2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.12 vm register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.13 memory_id0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.14 memory_id1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 memory blocks delailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 primary flash and secondary flash memo ry description . . . . . . . . . . . . 30 7.1.1 memory block selects signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1.2 ready/busy pin (pe4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1.3 memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1.4 power-up condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.5 reading flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1.6 programming flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1.7 unlock bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.8 erasing flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1.9 specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1.10 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1.11 reset (reset ) pin input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3 memory select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3.1 memory select configuration for mcus with separate program and data spaces 43 7.3.2 configuration modes for mcus with separate program and data spaces . 43 7.4 page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5 memory id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 plds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.1 decode pld (dpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2 general purpose pld (gpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 obsolete product(s) - obsolete product(s)
contents psd4135g2, psd4135g2v 4/104 doc id 7838 rev 2 9 mcu bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.1 psd interface to a multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2 psd interface to a non-multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.3 data byte enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.4 mcu interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.4.1 80c196 and 80c186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.4.2 mc683xx and 68hc16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.4.3 80c51xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.4.4 h8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.4.5 mmc2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.4.6 c16x family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1 general port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.2 port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.2.1 mcu i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2.2 pld i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2.3 address in mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2.4 data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.2.5 jtag isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.2.6 mcu reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.2.7 address out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.3 port configuration registers (pcrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.3.1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.3.2 direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.3.3 drive select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.4 port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.4.1 data in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.4.2 data out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.5 port a, b, and c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.6 port d ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.7 port e ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.8 port f ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.9 port g ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v contents doc id 7838 rev 2 5/104 11.1 automatic power-down (apd) unit and power-down mode . . . . . . . . . . . 72 11.1.1 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.1.2 other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.1.3 reset and power-on requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12 in-circuit programming using the jtag-i sp interface . . . . . . . . . . . . . 77 12.1 standard jtag signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.2 jtag extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3 security and flash memories protection . . . . . . . . . . . . . . . . . . . . . . . . . 78 13 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 15 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 16 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 17 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 appendix a pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 obsolete product(s) - obsolete product(s)
list of tables psd4135g2, psd4135g2v 6/104 doc id 7838 rev 2 list of tables table 1. pin names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. pld i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. jtag signals on port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. methods of programming different functional blocks of the psd . . . . . . . . . . . . . . . . . . . . 21 table 6. register address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. data-in registers - ports a, b, c, d, e, f, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. data-out registers - ports a, b, c, d, e, f, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. direction registers - ports a, b, c, d, e, f, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. control registers - ports e, f, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. drive registers - ports a, b, d, e, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. drive registers - ports c, f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. flash memory protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. flash boot protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15. page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16. pmmr0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. pmmr2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. vm register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 19. memory_id0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 20. memory_id1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 21. memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 table 22. instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 23. status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 24. status bits for motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 25. dpld and gpld inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 26. gpld product term availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 27. mcus and their control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 28. 16-bit data bus with bhe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 29. 16-bit data bus with wrh and wrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 30. 16-bit data bus with siz0, a0 (motorola mcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 31. 16-bit data bus with lds , uds (motorola mcu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 32. port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 33. port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 34. i/o port latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 35. port configuration registers (pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 36. port pin direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 37. port direction assignment example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 38. drive register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 39. port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 40. effect of power-down mode on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 table 41. psd timing and standby current during power-down mode . . . . . . . . . . . . . . . . . . . . . . . . 72 table 42. status during power-on reset, warm reset and power-down mode. . . . . . . . . . . . . . . . . . 76 table 43. jtag port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 44. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 45. example of psd typical power calculation at v cc = 5.0v (with turbo mode on) . . . . . . . . 82 table 46. example of psd typical power calculation at v cc = 5.0v (with turbo mode off) . . . . . . . . 84 table 47. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 48. ac signal letters for pld timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v list of tables doc id 7838 rev 2 7/104 table 49. ac signal behavior symbols for pld timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 50. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 51. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 52. dc characteristics 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 53. dc characteristics (3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 54. read timing (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 55. read timing (3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 56. write timing (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 57. write timing (3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 58. pld combinatorial timing (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 59. pld combinatorial timing (3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 60. power-down timing (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 61. power-down timing (3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 62. reset (reset ) timing (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 63. reset (reset ) timing (3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 64. program, write and erase timings (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 65. program, write and erase times (3 v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 66. isc timing (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 67. lqfp80 - 80-lead plastic thin, quad, flat package mechanical data. . . . . . . . . . . . . . . . . 100 table 68. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 69. psd4235g2 lqfp80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 70. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 obsolete product(s) - obsolete product(s)
list of figures psd4135g2, psd4135g2v 8/104 doc id 7838 rev 2 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. lqfp connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. psdsoft express development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 figure 6. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 7. data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 8. priority level of memory and i/o components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 9. 80c51xa memory modules - separate space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 10. 80c51xa memory modules - combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 11. page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 12. pld block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 13. dpld logic array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 14. the microcell and i/o port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 15. an example of a typical 16-bit multiplexed bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 16. an example of a typical 16-bit non-multiplexed bus interface. . . . . . . . . . . . . . . . . . . . . . . 53 figure 17. interfacing the psd4135g2 with an 80c196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 18. interfacing the psd with an mc68331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 figure 19. interfacing the psd with an 80c51xa-g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 20. interfacing a psd4135g2 with a h83/2350 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 21. interfacing a psd4135g2 with a mmc2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 22. interfacing a psd4135g2 with a c167r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 23. general i/o port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 24. port a, b, and c structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 25. port d structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 26. port e, f, and g structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 27. apd unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 28. enable power-down flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 29. power-on and warm reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 30. pld icc /frequency consumption - 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 31. pld icc /frequency consumption - 3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 32. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 33. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 34. switching waveforms - key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 35. read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 36. write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 37. input to output disable/enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 38. reset (reset ) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 39. isc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 40. lqfp80 - 80-lead plastic thin, quad, flat package outline . . . . . . . . . . . . . . . . . . . . . . . . 100 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v description doc id 7838 rev 2 9/104 1 description the psd4135g2 and psd4135g2v programmable microcontroller (mcu) peripherals bring in-system-programmability (isp) to flash memory and programmable logi c. the result is a simple and flexible solution for embedded designs. the devices combine many of the peripheral functions found in mcu based applications (see figure 1 ). they consist of six major types of functional blocks: memory blocks ? 4 mbit of flash memory ? a secondary flash memory for boot or data ? over 3,000 gates of flash programmable logic ? 64 kbit sram pld blocks bus interface reconfigurable i/o ports power management unit jtag-isp interface the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. the psd4135g2 and psd4135g2v devices offer two methods to program psd flash memory while the psd is soldered to a circuit board. figure 1. block diagram product(s) - obsolete product( obsolete product(s) - obsolete product(s)
description psd4135g2, psd4135g2v 10/104 doc id 7838 rev 2 1.1 in-system progra mming (isp) via jtag an ieee 1149.1 complia nt jtag-isp interface is included on the ps d enabling the entire device (both flash memories, the pld, and all configuration) to be rapidly programmed while soldered to the circuit board. this re quires no mcu particip ation, which means the psd can be programmed anytime, even while completely blank. the innovative jtag interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: 1.1.1 first time programming how do i get firmware into the flash the very first time? jtag is the answer, program the psd while blank with no mcu involvement. 1.1.2 inventory build-up of pre-programmed devices how do i maintain an accurate count of pre-programmed flash memory and pld devices based on customer demand? how many and what version? jtag is the answer, build your hardware with blank psds soldered directly to the board and then custom program just before they are shipped to customer. no more labels on chips and no more wasted inventory. 1.1.3 expensive sockets how do i eliminate the need for expensive and unreliable sockets? jtag is the answer. solder the psd directly to the circuit board. program first time and subsequent times with jtag. no need to handle devices and bend the fragile leads. 1.2 in-application programming (iap) two independent flash memory arrays are included so the mcu can execute code from one memory while erasing and programming the other. robust product firmware updates in the field are possible over any communication channel (can, ethernet, uart, j1850, etc) using this unique architecture. designers are relieved of these problems: 1.2.1 simultaneous read and write to flash memory how can the mcu program the same memory from which it is executing code? it cannot. the psd allows the mcu to operate the two flash memories concurrently, reading code from one while erasing and programming the other during iap. 1.2.2 complex memory mapping how can i map these two memories efficiently? a programmable decode pld is embedded in the psd. the concurrent psd memories can be mapped anywhere in mcu address space, segment by segment with extremely high address resolution. as an option, the secondary flash memory can be swapped out of the system memory map when iap is complete. a built-in page register breaks the mcu address limit. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v description doc id 7838 rev 2 11/104 1.2.3 separate program and data space how can i write to flash memory while it resides in ?program? space during field firmware updates? my 80c51xa won?t allow it. the flas h psd provides means to ?reclassify? flash memory as ?data? space during iap, then back to ?program? space when complete. 1.2.4 psdsoft? express psdsoft express, a software development tool from st, guides you through the design process step-by-step making it possible to complete an embedded mcu design capable of isp/iap in just hours. select your mcu and psdsoft express takes you through the remainder of the design with point and click entry, covering psd selection, pin definitions, programmable logic inputs and outpus, mcu memory map definition, ansi-c code generation for your mcu, and merging your mcu firmware with the psd design. when complete, two different device programmers are supported directly from psdsoft express: flashlink (jtag) and psdpro. figure 2. logic diagram ai04916 16 ad0-ad15 pf0-pf7 v cc psd4xxxgx v ss 8 pg0-pg7 8 pb0-pb7 8 pa0-pa7 8 3 cntl0- cntl2 reset pd0-pd3 4 pc0-pc7 8 pe0-pe7 8 obsolete product(s) - obsolete product(s)
description psd4135g2, psd4135g2v 12/104 doc id 7838 rev 2 table 1. pin names pin description pa 0 - pa 7 po r t - a pb0-pb7 port-b pc0-pc7 port-c pd0-pd3 port-d pe0-pe7 port-e pf0-pf7 port-f pg0-pg7 port-g ad0-ad15 address/data cntl0-cntl2 control reset reset v cc supply voltage v ss ground obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v description doc id 7838 rev 2 13/104 figure 3. lqfp connections obsolete product(s) 60 cntl1 59 cntl0 58 pa7 57 pa6 56 pa5 55 pa4 54 pa3 53 pa2 52 pa1 51 pa0 50 gnd 49 gnd 48 pc7 47 pc6 46 pc5 45 pc4 44 pc3 43 pc2 42 pc1 41 pc0 pd2 pd3 ad0 ad1 ad2 ad3 ad4 gnd v cc ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pd1 pd0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 gnd v cc pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 v cc gnd pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 reset cntl2 obsolete product(s) - obsolete product(s)
pin description psd 4135g2, psd4135g2v 14/104 doc id 7838 rev 2 2 pin description ta bl e 2 describes the pin names and pin functions of the psd4135g2 and psd4135g2v. pins that have multiple names and/or functions are defined using psdsoft express. table 2. pin description pin name pin type description adio0- adio7 3-7 10-12 i/o this is the lower address/data port. c onnect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/da ta bus where the data is multiplexed with the lower address bits, connect ad0-ad7 to this port. 2. if your mcu does not have a multiplexed address/data bus, connect a0-a7 to this port. 3. if you are using an 80c51xa in burst mode, connect a4/d0 through a11/d7 to this port. ale or as latches the address. the psd driv es data out only if the read signal is active and one of the psd functional blocks has been selected. the addresses on this port are passed to the plds. adio8- adio15 13-20 i/o this is the upper address/data port. co nnect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/da ta bus where the data is multiplexed with the upper address bits, connect a8-a15 to this port. 2. if your mcu does not have a multiplexed address/data bus, connect a8-a15 to this port. 3. if you are using an 80c51xa in burst mode, connect a12/d8 through a19/d15 to this port. ale or as latches the address. the psd driv es data out only if the read signal is active and one of the psd functional blocks has been selected. the addresses on this port are passed to the plds. cntl0 59 i the following control signals can be connected to this pin, based on your mcu: 1. wr - active low, write strobe input. 2. r_w - active high, read/active low write input. 3. wrl - active low, write to low-byte. this pin is connected to the plds. theref ore, these signals can be used in decode and other logic equations. cntl1 60 i the following control signals can be connected to this pin, based on your mcu: 1. rd - active low, read strobe input. 2. e - e clock input. 3. ds - active low, data strobe input. 4. lds - active low, strobe for low data byte. this pin is connected to the plds. theref ore, these signals can be used in decode and other logic equations. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v pin description doc id 7838 rev 2 15/104 cntl2 40 i read or other control input pin, with mu ltiple configurations. depending on the mcu interface selected, this pin can be: 1. psen - program select enable, active low in code fetch bus cycle (80c51xa mode). 2. bhe - high-byte enable, 16-bit data bus. 3. uds - active low, strobe for high data byte, 16-bit data bus mode. 4. siz0 - byte enable input. 5. lstrb - low strobe input. this pin is also connected to the plds. reset 39 i active low input. resets i/o ports, pld macrocells and some of the configuration registers and jtag registers. must be low at power-up. reset also aborts any flash memory program or erase cycle that is currently in progress. pa 0 - pa 7 5 1 - 5 8 i/o cmos or open drain these pins make up port a. these port pins are configurable and can have the following functions: 1. mcu i/o - standard output or input port. 2. gpld macrocell outputs. 3. latched, transparent or registered pld inputs (can also be pld input for address a16 and above). pb0-pb7 61-68 i/o cmos or open drain these pins make up port b. these port pins are configurable and can have the following functions: 1. mcu i/o - standard output or input port. 2. gpld macrocell outputs. 3. latched, transparent or registered pld inputs (can also be pld input for address a16 and above). pc0-pc7 41-48 i/o cmos or slew rate these pins make up port c. these port pins are configurable and can have the following functions: 1. mcu i/o - standard output or input port. 2. external chip select (ecs0-ecs7) outputs. 3. latched, transparent or registered pld inputs (can also be pld input for address a16 and above). pd0 79 i/o cmos or open drain pd0 pin of port d. this port pin can be configured to have the following functions: 1. ale/as input - latches address on adio0-adio15. 2. as input - latches address on adio0-adio15 on the rising edge. 3. mcu i/o - standard output or input port. 4. transparent pld input (can also be pld input for address a16 and above). pd1 80 i/o cmos or open drain pd1 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. transparent pld input (can also be pld input for address a16 and above). 3. clkin - clock input to the gpld macrocells, the apd unit?s power-down counter, and the gpld and array. table 2. pin description (continued) pin name pin type description obsolete product(s) - obsolete product(s)
pin description psd 4135g2, psd4135g2v 16/104 doc id 7838 rev 2 pd2 1 i/o cmos or open drain pd2 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. transparent pld input (can also be pld input for address a16 and above). 3. psd chip select input (csi ). when low, the mcu can access the psd memory and i/o. when high, the psd memory blocks are disabled to conserve power. the falling edge of this signal can be used to get the device out of power-down mode. pd3 2 i/o cmos or open drain pd3 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. transparent pld input (can also be pld input for address a16 and above). 3. wrh - for 16-bit data bus, write to high byte, active low. pe0 71 i/o cmos or open drain pe0 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. tms input for the jtag serial interface. pe1 72 i/o cmos or open drain pe1 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. tck input for the jtag serial interface. pe2 73 i/o cmos or open drain pe2 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. tdi input for the jtag serial interface. pe3 74 i/o cmos or open drain pe3 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. tdo output for the jtag serial interface. pe4 75 i/o cmos or open drain pe4 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. tstat output for the jtag serial interface. 4. ready/busy output for parallel in- system programming (isp). pe5 76 i/o cmos or open drain pe5 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. terr active low output for the jtag serial interface. pe6 77 i/o cmos or open drain pe6 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. table 2. pin description (continued) pin name pin type description obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v pin description doc id 7838 rev 2 17/104 pe7 78 i/o cmos or open drain pe7 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. pf0-pf7 31-38 i/o cmos or open drain these pins make up port f. these port pins are configurable and can have the following functions: 1. mcu i/o - standard output or input port. 2. inputs to gpld. 3. latched address outputs. 4. address a1-a3 inputs in 80c51xa mode (pf0 is grounded) 5. data bus port (d0-d7) in a non-multiplexed bus configuration. 6. mcu reset mode. pg0-pg7 21-28 i/o cmos or open drain these pins make up port g. these port pins are configurable and can have the following functions: 1. mcu i/o - standard output or input port. 2. latched address outputs. 3. data bus port (d8-d15) in a non-multiplexed bus configuration. 4. mcu reset mode. v cc 9, 29, 69 supply voltage gnd 8, 30, 49, 50, 70 ground pins table 2. pin description (continued) pin name pin type description obsolete product(s) - obsolete product(s)
pin description psd 4135g2, psd4135g2v 18/104 doc id 7838 rev 2 figure 4. detailed block diagram 1. additional address lines can be brought in to psd via port a, b, c, d, or f. prog. mcu bus intrf. adio port cntl0, cntl1, cntl2 ad0 ? ad15 * pld input bus prog. port port a prog. port port b 4 mbit main flash memory 8 sectors pa0 ? pa7 prog. port port f prog. port port g prog. port port e pb0 ? pb7 prog. port port c prog. port port d pf0 ? pf7 pg0 ? pg7 pe0 ? pe7 pc0 ? pc7 pd0 ? pd3 address/data/control bus 66 66 256 kbit secondary flash memory (boot or data) 4 sectors 64 kbit sram runtime control and i/o registers sram select gpld output gpld output gpld output i/o port pld input csiop flash isp pld (gpld) flash decode pld ( dpld ) pld, configuration & flash memory loader jtag serial channel page register embedded algorithm sector selects sector selects global config. & security obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v psd architectural overview doc id 7838 rev 2 19/104 3 psd architectural overview psd4135g2 and psd4135g2v devices contain several major functional blocks. figure 4: detailed block diagram shows the architecture of the device family. the functions of each block are described briefly in the following sections. many of the blocks perform multiple functions and are user configurable. 3.1 memory the devices contain the following memories: 4 mbit flash a secondary 256 kbit flash memory for boot or data 64 kbit sram. the 4 mbit flash is the main memory of the psd4135g2/g2v. it is divided into eight equally-sized sectors that are individually selectable. the 256 kbit secondary flash memory is divided into four equally-sized sectors. each sector is individually selectable. the 64 kbit sram is intended for use as a scratchpad memory or as an extension to the microcontroller sram. each block of memory can be located in a different address space as defined by the user. the access times for all memory types includes the address latching and dpld decoding time. 3.2 plds the device contains two pld blocks, each optimized for a different function, as shown in ta bl e 3 . the functional partitioning of the plds reduces power consumption, optimizes cost/performance, and eases design entry. the decode pld (dpld) is used to decode addresses and generate chip selects for the psd4135g2/g2v internal memory and registers. the general purpose pld (gpld) can implement user-defined external chip selects and logic functions. the plds receive their inputs from the pld input bus and are differentiated by their output destinations, number of product terms. the plds consume minimal power by using zero-power design techniques. the speed and power consumption of the pld is controlled by the turbo bit in the pmmr0 register and other bits in the pmmr2 registers. these registers are set by the microcontroller at runtime. there is a slight penalty to pld propagation time when invoking the non-turbo bit. obsolete product(s) - obsolete product(s)
psd architectural overview psd4135g2, psd4135g2v 20/104 doc id 7838 rev 2 3.3 i/o ports the psd4135g2 and psd4135g2v have 52 i/o pins divided among seven ports (port a, b, c, d, e, f and g). each i/o pin can be individually configured for different functions. ports can be configured as standard mcu i/o ports, pld i/o, or latched address outputs for microcontrollers using multiplexed address/data busses. the jtag pins can be enabled on port e for in-system programming (isp). ports f and g can also be configured as a data port for a non-multiplexed bus. 3.4 mcu bus interface the psd4135g2 and psd4135g2v easily interface with most 16-bit microcontrollers that have either multiplexed or non-multiplexed address/data busses. the devices are configured to respond to the microcontroller?s control signals, which are also used as inputs to the plds. 3.5 isp via jtag port in-system programming can be performed through the jtag pins on port e. this serial interface allows complete programming of the entire psd4135g2/g2v devices. a blank device can be completely programmed. the jtag signals (tms, tck, tstat, terr , tdi, tdo) can be multiplexed with other functions on port e. ta bl e 4 indicates the jtag signals pin assignments. table 3. pld i/o name inputs outputs product terms decode pld (dpld) 66 14 40 general purpose pld (gpld) 66 24 136 table 4. jtag signals on port e port e pins jtag signal pe0 tms pe1 tck pe2 tdi pe3 tdo pe4 tstat pe5 terr obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v psd architectural overview doc id 7838 rev 2 21/104 3.6 in-system programming (isp) using the jtag signals on port e, the entire psd4135g2/g2v (memory, logic, configuration) devices can be programmed or erased without the use of the microcontroller. 3.7 in-application programming (iap) the main flash memory can also be programmed in-system by the microcontroller executing the programming algorithms out of the secondary flash memory, or sram. since this is a sizable separate block, the application can also continue to operate. the secondary flash boot memory can be programmed the same way by executing out of the main flash memory. ta bl e 5 indicates which programming methods can program different functional blocks of the psd4135g2/g2v. 3.8 page register the eight-bit page register expands the address range of the microcontroller by up to 256 times.the paged address can be used as part of the address space to access external memory and peripherals or internal memory and i/o. the page register can also be used to change the address mapping of blocks of flash memory into different memory spaces for iap. 3.9 power management unit (pmu) the power management unit (pmu) in the psd4135g2/g2v gives the user control of the power consumption on selected functional blocks based on system requirements. the pmu includes an automatic power-do wn unit (apd) that will turn off device functions due to microcontroller inactivity. the apd unit has a power-down mode that helps reduce power consumption. the psd4135g2 and psd4135g2v also have some bits that are configured at run-time by the mcu to reduce power consumption of the gpld. the turbo bit in the pmmr0 register can be turned off and the gpld will latch its outputs and go to standby until the next transition on its inputs. additionally, bits in the pmmr2 register can be set by the mcu to block signals from entering the gpld to reduce power consumption (see section 11: power management ). table 5. methods of programming different functional blocks of the psd functional block jtag-isp device programmer iap primary flash memory yes yes yes secondary flash memory yes yes yes pld array (dpld and gpld) yes yes no psd configuration yes yes no obsolete product(s) - obsolete product(s)
development system psd4135g2, psd4135g2v 22/104 doc id 7838 rev 2 4 development system the psd4135g2/g2v series is supported by psdsoft a windows-based (95, 98, nt) software development tool. a psd design is quickly and easily produced in a point and click environment. the designer does not need to enter hardware definition language (hdl) equations (unless desired) to define psd pin functions and memory map information. the general design flow is shown in figure 5 below. psdsoft is available from our web site (www.psdst.com) or other distribution channels. psdsoft directly supports two low cost device programmers from st, psdpro and flashlink (jtag). both of these programmers may be purchased through your local rep/distributor, or directly from our web site using a credit card. the psd4135g2 and psd4135g2v are also supported by third party device programmers, see web site for current list. figure 5. psdsoft express development tool merge mcu firmware with psd configuration psd programmer *.obj file psdpro, or flashlink (jtag) a composite object file is created containing mcu firmware and psd configuration c code generation generate c code specific to psd functions user's choice of microcontroller compiler/linker *.obj file available for 3rd party programmers (conventional or jtag-isc) mcu firmware hex or s-record format ai04919 define general purpose logic in cpld point and click definition of combin- atorial and registered logic in cpld. access hdl is available if needed define psd pin and node functions point and click definition of psd pin functions, internal nodes, and mcu system memory map choose mcu and psd automatically configures mcu bus interface and other psd attributes obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v psd register description and address offsets doc id 7838 rev 2 23/104 5 psd register description and address offsets ta bl e 6 shows the offset addresses to the psd registers relative to the csiop base address. the csiop space is the 256 bytes of ad dress that is allocated by the user to the internal psd registers. ta b l e 6 provides brief descriptions of the registers in csiop space. the following sections give a more detailed description. table 6. register address offset register name port a port b port c port d port e port f port g other (1) description data in 00 01 10 11 30 40 41 reads port pin as input, mcu i/o input mode control 32 42 43 selects mode between mcu i/o or address out data out 04 05 14 15 34 44 45 stores data for output to port pins, mcu i/o output mode direction 06 07 16 17 36 46 47 configures port pin as input or output drive select 08 09 18 19 38 48 49 configures port pins as either cmos or open drain on some pins, while selecting high slew rate on other pins. flash memory protection c0 read only - primary flash sector protection flash boot protection c2 read only - psd security and secondary flash memory sector protection pmmr0 b0 power management register 0 pmmr2 b4 power management register 2 page e0 page register vm e2 places psd memory areas in program and/or data space on an individual basis. memory_id0 f0 read only - sram and primary memory size memory_id1 f1 read only - secondary memory type and size 1. other registers that are not part of the i/o ports. obsolete product(s) - obsolete product(s)
register bit definition psd4135g2, psd4135g2v 24/104 doc id 7838 rev 2 6 register bit definition all the registers in the psd4135g2/g2v are included here for reference. detail description of the registers are found in the functional block sections of the datasheet. 6.1 data-in registers - port a, b, c, d, e, f, g read port pin status when port is in mcu i/o input mode. read-only registers. 6.2 data-out registers - port a, b, c, d, e, f, g latched data for output to port pin when pin is configured in mcu i/o output mode. 6.3 direction registers - ports a, b, c, d, e, f, g port pin : 0: port pin is configured in input mode (default). 1: port pin is configured in output mode. 6.4 control registers table 7. data-in registers - ports a, b, c, d, e, f, g bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 table 8. data-out registers - ports a, b, c, d, e, f, g bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 table 9. direction registers - ports a, b, c, d, e, f, g bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 table 10. control registers - ports e, f, g bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v register bit definition doc id 7838 rev 2 25/104 port pin : 0: port pin is configured in mcu i/o mode (default). 1: port pin is configured in latched address out mode. 6.5 drive registers - ports a, b, d, e, g port pin : 0: port pin is configured for cmos output driver (default). 1: port pin is configured for open drain output driver. 6.6 drive registers - ports c and f port pin : 0: port pin is configured for cmos output driver (default). 1: port pin is configured in slew rate mode. 6.7 flash memory protection register read-only register sec_prot: 1: primary flash memory sector is write protected. 0: primary flash memory sector is not write protected. table 11. drive registers - ports a, b, d, e, g bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 table 12. drive registers - ports c, f bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 table 13. flash memory protection register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot obsolete product(s) - obsolete product(s)
register bit definition psd4135g2, psd4135g2v 26/104 doc id 7838 rev 2 6.8 flash boot protection register sec_prot: 1: secondary flash memory sector is write protected. 0: secondary flash memory sector is not write protected. security_bit: 0: security bit in device has not been set. 1: security bit in device has been set. 6.9 page register this register configures the page input to pld. default value is pgr7-pgr0=0. 6.10 pmmr0 register the bits of this register ar e cleared to zero following power-up. subsequent reset (reset ) pulses do not clear the registers. apd enable: 0: automatic power-down (apd) is disabled. 1: automatic power-down (apd) is enabled. pld turbo: 0: pld turbo is on. 1: pld turbo is off, saving power. table 14. flash boot protection register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 security_ bit not used not used not used sec3_prot sec2_prot sec1_prot sec0_prot table 15. page register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pgr 7 pgr 6 pgr 5 pgr 4 pgr 3 pgr 2 pgr 1 pgr 0 table 16. pmmr0 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not used (set to ?0?) not used (set to ?0?) not used (set to ?0?) pld array clk pld tu r b o not used (set to ?0?) apd enable not used (set to ?0?) obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v register bit definition doc id 7838 rev 2 27/104 pld array clk: 0: clkin to the pld and array is connected. every clkin change powers up the pld when turbo bit is off. 1: clkin to the pld and array is disconnected, saving power. 6.11 pmmr2 register for bit 4, bit 3, bit 2: see ta b l e 2 7 for the signals that are blocked on pins cntl0-cntl2. pld array addr: 0: address a7-a0 are connected to the pld array. 1 address a7-a0 are blocked from the pld array, saving power. note: in xa mode, a3-a0 come from pf3-pf0, and a7-a4 come from adio7-adio4). pld array cntl2: 0: cntl2 input to the pld and array is connected. 1: cntl2 input to the pld and array is disconnected, saving power. pld array cntl1 0: cntl1 input to the pld and array is connected. 1: cntl1 input to the pld and array is disconnected, saving power. pld array cntl0 0: cntl0 input to the pld and array is connected. 1: cntl0 input to the pld and array is disconnected, saving power. pld array ale 0: ale input to the pld and array is connected. 1: ale input to the pld and array is disconnected, saving power. pld array wrh 0: wrh /dbe input to the pld and array is connected. 1: wrh /dbe input to the pld and array is disconnected, saving power. table 17. pmmr2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not used (set to ?0?) pld array wrh pld array ale pld array cntl2 pld array cntl1 pld array cntl0 not used (set to ?0?) pld array addr obsolete product(s) - obsolete product(s)
register bit definition psd4135g2, psd4135g2v 28/104 doc id 7838 rev 2 6.12 vm register on reset, bit1-bit4 are loaded to configurations that are selected by the user in psdsoft express. bit0 and bit7 are always cleared on rese t. bit0-bit4 are active only when the device is configured in philips 80c51xa mode. sr_code 0 = psen cannot access sram in 80c51xa modes. 1 = psen can access sram in 80c51xa modes. boot_code 0 = psen cannot access secondary nvm in 80c51xa modes. 1 = psen can access secondary nvm in 80c51xa modes. fl_code 0 = psen cannot access primary flash memory in 80c51xa modes. 1 = psen can access primary flash memory in 80c51xa modes. boot_data 0 = rd cannot access secondary nvm in 80c51xa modes. 1 = rd can access secondary nvm in 80c51xa modes. fl_data 0 = rd cannot access primary flash memory in 80c51xa modes. 1 = rd can access primary flash memory in 80c51xa modes. peripheral mode 0 = peripheral mode of port f is disabled. 1 = peripheral mode of port f is enabled. table 18. vm register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 peripheral mode not used (set to ?0?) not used (set to ?0?) fl_data boot_data fl_code boot_code sr_code obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v register bit definition doc id 7838 rev 2 29/104 6.13 memory_id0 registers f_size[3:0] 0h = there is no primary flash memory 1h: primary flash memory size is 256 kbit 2h: primary flash memory size is 512 kbit 3h = primary flash memory size is 1 mbit 4h = primary flash memory size is 2 mbit 5h = primary flash memory size is 4 mbit 6h = primary flash memory size is 8 mbit s_size[3:0] 0h = there is no sram 1h = sram size is 16 kbit 2h = sram size is 32 kbit 3h = sram size is 64 kbit 4h = sram size is 128 kbit 5h = sram size is 256 kbit 6.14 memory_id1 register b_size[3:0] 0h = there is no secondary nvm 1h = secondary nvm size is 128 kbit 2h = secondary nvm size is 256 kbit 3h = secondary nvm size is 512 kbit b_type[1:0] 0h = secondary nvm is flash memory 1h = secondary nvm is eeprom table 19. memory_id0 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s_size 3 s_size 2 s_size 1 s_size 0 f_size 3 f_size 2 f_size 1 f_size 0 table 20. memory_id1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not used (set to ?0?) not used (set to ?0?) b_type 1 b_type 0 b_size 3 b_size 2 b_size 1 b_size 0 obsolete product(s) - obsolete product(s)
memory blocks delailed operation psd4135g2, psd4135g2v 30/104 doc id 7838 rev 2 7 memory blocks delailed operation the psd4135g2 and psd4135g2v have the following memory blocks: the main flash memory secondary flash memory sram. the memory select signals for these blocks originate from the decode pld (dpld) and are user-defined in psdsoft. ta bl e 2 1 summarizes which versions of the psd4135g2/g2v contain which memory blocks. 7.1 primary flash and secondar y flash memory description the primary flash memory block is divided evenly into eight sectors. the secondary flash memory is divided into four sectors of eight kbytes each. each sector of either memory can be separately protected from program and erase operations. flash memory may be erased on a sector-by-sector basis and programmed word-by-word. flash sector erasure may be suspended while data is read from other sectors of memory and then resumed after reading. during a program or erase of flash, the status can be output on the rdy/bsy pin of port pe4. this pin is set up using psdsoft express. table 21. memory block size and organization sector number primary flash memory secondary flash memory sram sector size (x16, kbytes) sector select signal sector size (x16, kbytes) sector select signal sram size (x16, kbytes) sram select signal 0 32 fs0 4 csboot0 4 rs0 1 32 fs1 4 csboot1 2 32 fs2 4 csboot2 3 32 fs3 4 csboot3 432 fs4 532 fs5 632 fs6 732 fs7 total 512 kbytes 8 sectors 64 kbytes 4 sectors 8 kbytes obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v memory blocks delailed operation doc id 7838 rev 2 31/104 7.1.1 memory block selects signals the decode pld in the psd4135g2/g2v generates the chip selects for all the internal memory blocks (refer to section 8: plds ). each of the eight flash memory sectors have a flash select signal (fs0-fs7) which can contain up to three product terms. each of the four secondary flash memory sectors have a select signal (csboot0-3) which can contain up to three product terms. having three product terms for each sector select signal allows a given sector to be mapped in different areas of system memory. when using a microcontroller (80c51xa) with separate program and data space, these flexible select signals allow dynamic re-mapping of sectors from one space to the other before and after iap. 7.1.2 ready/busy pin (pe4) pin pe4 can be used to output the ready/busy status of the psd4135g2/g2v. the output on the pin will be a ?0? (busy) when fl ash memory blocks are being written to, or when the flash memory block is being erased. the output will be a ?1? (ready) when no write or erase operation is in progress. 7.1.3 memory operation the primary flash and secondary flash memories are addressed through the microcontroller interface on the psd4135g2g2v devices. the microcontroller can access these memories in one of two ways: the microcontroller can execute a typical bus write or read operation just as it would if accessing a ram or rom device using standard bus cycles. the microcontroller can execute a specific instruction that consists of several write and read operations. this involves writing specif ic data patterns to special addresses within the flash to invoke an embedded algorithm. these instructions are summarized in ta bl e 2 2 . typically, flash memory can be read by the microcontroller using read operations, just as it would read a rom device. however, flash memory can only be erased and programmed with specific instructions. for example, the microcontroller cannot write a single word directly to flash memory as one would write a word to ram. to program a word into flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event. this status test is achieved by a read operation or polling the rdy/busy pin (pe4). the flash memory can also be read by using special instructions to retrieve particular flash device information (sector protect status and id). instructions an instruction is defined as a sequence of s pecific operations. each received byte is sequentially decoded by the psd and not executed as a standard write operation. the instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. some instructions are structured to include read operations after the initial write operations. the sequencing of any instruction must be followed exactly. any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing flash memory will reset the device logic into a read array mode (flash memory reads like a rom device). obsolete product(s) - obsolete product(s)
memory blocks delailed operation psd4135g2, psd4135g2v 32/104 doc id 7838 rev 2 the psd4135g2/g2v main flash and secondar y flash support these instructions (see ta bl e 2 2 ): erase memory by chip or sector suspend or resume sector erase program a word reset to read array mode read main flash identifier value read sector protection status bypass instruction these instructions are detailed in ta bl e 2 2 . for efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. the coded cy cles consist of writing the da ta byte aah to address xaaah during the first cycle and data byte 55h to address x554h during the second cycle (unless the bypass instruction feature is used). address lines a15-a12 are don?t care during the instruction write cycles. however, the appropriate sector select signal (fsi or csbooti) must be selected. the main flash and the secondary flash block have the same set of instructions (except read main flash id). the chip selects of the flash memory will determine which flash will receive and execute the instruction. the main flash is selected if any one of the fs0-7 is active, and the secondary flash block is selected if any one of the csboot0-3 is active. table 22. instructions (1)(2)(3) instruction (4) fs0-fs7 or csboot0- csboot3 (5) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read (6) 1 ?read? rd @ ra read main flash id (7) 1 aah@ xaaah 55h@ x554h 90h@ xaaah read id @ xx02h read sector protection (7)(8) (9) 1 aah@ xaaah 55h@ x554h 90h@ xaaah read 00h or 01h @ xx04h program a flash word (9) 1 aah@ xaaah 55h@ x554h a0h@ xaaah pd@ pa flash sector erase (10)(9) 1 aah@ xaaah 55h@ x554h 80h@ xaaah aah@ xaaah 55h@ x554h 30h@ sa 30h (10) @ next sa flash bulk erase (9) 1 aah@ xaaah 55h@ x554h 80h@ xaaah aah@ xaaah 55h@ x554h 10h@ xaaah suspend sector erase (11) 1 b0h@ xxxxh resume sector erase (12) 1 30h@ xxxxh reset (7) 1 f0h@ xxxxh obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v memory blocks delailed operation doc id 7838 rev 2 33/104 unlock bypass 1 aah@ xaaah 55h@ x554h 20h@ xaaah unlock bypass program (13) 1 a0h@ xxxxh pd@ pa unlock bypass reset (14) 1 90h@ xxxxh 00h@ xxxxh 1. all bus cycles are write bus cycles, except the ones with the ?read? label 2. all values are in hexadecimal: x = don?t care. addresses of the form xxxxh, in this table, must be even addresses, ra = address of the memory location to be read rd = data read from location ra during the read cycle pa = address of the memory location to be programmed. addresses are latched on the falling edge of write strobe (wr , cntl0). pa is an even address fo r psd in word programming mode. pd = data word to be programmed at location pa. data is latched on the rising edge of write strobe (wr , cntl0) sa = address of the sector to be erased or verified. the sector select (fs0-fs7 or csboot0-csboot3) of the sector to be erased, or verified, must be active (high). 3. only address bits a1 1-a0 are used in instruction decoding. 4. all write bus cycles in an instruction are byte write to an even address (xa4ah or x554h). a flash memory program bus cycle writes a word to an even address. 5. sector select (fs0 to fs7 or csbo ot0 to csboot3) signals are active high, and are defined in psdsoft express. 6. no unlock or instruction cycles are r equired when the device is in the read mode. 7. the reset instruction is required to return to the read mode after reading the flash id, or after reading the sector protection status, or if the er ror flag bit (dq5/dq13) goes high. 8. the data is 00h for an unprotected sector, and 01h for a protected sector. in the fourth cycle, the sector select is active, and (a1,a0)=(1,0) 9. the mcu cannot invoke these instructions while executing code from the same flash memory as that for which the instruction is intended. the mcu must fetch, for example, the code from the secondary flash memory when reading the sector protection status of the primary flash memory. 10. additional sectors to be erased must be written at the end of the sector erase instruction within 80s. 11. the system may perform read and program cycles in non- erasing sectors, read the flash id or read the sector protection status when in the suspend sector erase mode. the suspend sector erase instruction is valid only during a sector erase cycle. 12. the resume sector erase instruction is valid only during the suspend sector erase mode. 13. the unlock bypass instruction is required prior to the unlock bypass program instruction. 14. the unlock bypass reset flash instruction is required to retu rn to reading memory data when the device is in the unlock bypass mode. table 22. instructions (1)(2)(3) (continued) instruction (4) fs0-fs7 or csboot0- csboot3 (5) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 obsolete product(s) - obsolete product(s)
memory blocks delailed operation psd4135g2, psd4135g2v 34/104 doc id 7838 rev 2 7.1.4 power-up condition the psd4135g2/g2v internal logic is reset upon power-up to the read array mode. the fsi and csbooti select signals, along with the write strobe signal, must be in the false state during power-up for maximum security of the da ta contents and to remove the possibility of data being written on the first edge of a write strobe signal. any write cycle initiation is locked when v cc is below v lko . 7.1.5 reading flash memory under typical conditions, the microcontroller may read the flash, or secondary flash memories using read operations just as it would a rom or ram device. alternately, the microcontoller may use read operations to obtain status information about a program or erase operation in progress. lastly, the microcontroller may use instructions to read special data from these memories. the following sections describe these read functions. reading memory content primary flash and secondary flash memories are placed in the read array mode after power-up, chip reset, or a reset flash instruction (see ta b l e 2 2 ). the microcontroller can read the memory contents of primary flash or secondary flash by using read operations any time the read operation is not part of an instruction. reading primary flash identifier the primary flash identifier is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see ta b l e 2 2 ). the psd4135g2/g2v primary flash memory id is e8h. the secondary flash does not support this instruction. reading memory sector protection status the flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see ta bl e 2 2 ). the read operation will produce 01h if the flash sector is protected, or 00h if the sector is not protected. the sector protection status for all nvm blocks (primary flash or secondary flash) can also be read by the microcontroller accessing the flash protection and flash boot protection registers in psd i/o space. see section 6.7: flash memory protection register and section 6.8: flash boot protection register . reading the erase/program status bits the psd4135g2 and psd4135g2v provide several status bits to be used by the microcontroller to confirm the completion of an erase or programming instruction of flash memory. these status bits minimize the time that the microcontroller spends performing these tasks and are defined in ta b l e 2 3 . the status byte resides in even location and can be read as many times as needed. please note dq15-8 is even byte for motorola mcus with 16 bit data bus. for flash memory, the microcontroller can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. refer to section 7.1.6: programming flash memory for details. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v memory blocks delailed operation doc id 7838 rev 2 35/104 data polling flag dq7 (dq15 for motorola) when erasing or programming the flash memory bit dq7 (dq15) outputs the complement of the bit being entered for programming/writing on dq7 (dq15). once the program instruction or the write operation is completed, the true logic value is read on dq7 (dq15) (in a read operation). flash memory specific features: data polling is effective after the fourth writ e pulse (for programmin g) or after the sixth write pulse (for erase). it must be performed at the address being programmed or at an address within the flash sector being erased. during an erase instruction, dq7 (dq15) outputs a ?0?. after completion of the instruction, dq7 (dq15) will outp ut the last bit programmed (it is a ?1? after erasing). if the location to be programmed is in a protected flash sector, the instruction is ignored. if all the flash sectors to be erased are protected, dq7 (dq15) will be set to ?0? for about 100 s, and then return to the prev ious addressed location. no erasure will be performed. toggle flag dq6 (dq14 for motorola) the psd4135g2 and psd4135g2v offer another way for determining when the flash memory program instruction is completed. during the internal write operation and when either the fsi or csbooti is true, the dq6 (dq14) will toggle from ?0? to ?1? and ?1? to ?0? on subsequent attempts to read any word of the memory. when the internal cycle is complete, the togg ling will stop and the data read on the data bus is the addressed memory location. the device is now accessible for a new read or write operation. the operation is finished when two successive reads yield the same output data. flash memory specific features: the toggle bit is effective after the fourth write pulse (for programming) or after the sixth write pulse (for erase). if the location to be programmed belongs to a protected flash sector, the instruction is ignored. if all the flash sectors selected for erasure are protected, dq6 (dq1 4) will toggle to ?0? for about 100 s and then return to the previous addressed location. table 23. status bits dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 data polling toggle flag error flag x erase timeout xxx table 24. status bits for motorola (1)(2)(3) 1. x = not guaranteed value, c an be read either 1 or 0. 2. dq15-dq0 represent the data bus bits, d15-d0. 3. fs0-fs7/csboot0-csboot3 are active high. dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 data polling toggle flag error flag x erase timeout xxx obsolete product(s) - obsolete product(s)
memory blocks delailed operation psd4135g2, psd4135g2v 36/104 doc id 7838 rev 2 error flag dq5 (dq14 for motorola) during a normal program or erase cycle, the erro r bit will set to ?0?. this bit is set to ?1? when there is a failure during flash programming, sector erase, or bulk erase. in the case of flash programming, the error bit indicates the attempt to program a flash bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation. the error bit may also indicate a timeout condition while attempting to program a word. in case of an error in flash sector erase or word program, the flash sector in which the error occurred or to which the programmed location belongs must no longer be used. other flash sectors may still be used. the erro r bit resets after the reset in struction. a reset instruction is required after detecting the error bit. erase timeout flag dq3 (dq11 for motorola) the erase timer bit reflects the timeout period allowed between two consecutive sector erase instructions. the erase timer bit is set to ?0? after a sector erase instruction for a time period of 100 s + 20% unless an additional sector erase instruction is decoded. after this time period or when the additional sector erase instruction is decoded, dq3 (dq11) is set to ?1?. a rese t instruction is required after detecting the erase timer bit. 7.1.6 programming flash memory flash memory must be erased prior to being programmed. the mcu may erase flash memory all at once or by-sector. flash memory sector erases to all logic ones, and its bits are programmed to logic zeros. although erasing flash memory occurs on a sector or chip basis, programming flash memory occurs on a word basis. the psd4135g2/g2v primary flash and secondary flash memories require the mcu to send an instruction to program a word or perform an erase function (see ta bl e 2 2 ). once the mcu issues a flash memory program or erase instruction, it must check for the status of completion. the embedded algorithms that are invoked inside the psd4135g2/g2v support several means to provide status to the mcu. status may be checked using any of three met hods: data polling, data togg le, or the ready/busy output pin. data polling polling on dq7 (dq15) is a method of checking whether a program or erase instruction is in progress or ha s completed. figure 6 shows the data polling algorithm. when the mcu issues a programming instruction, the embedded algorithm within the psd4135g2/g2v begins. the mcu then reads the location of the word to be programmed in flash to check status. data bit dq7 (dq15) of this location becomes the compliment of data bit 7of the original data word to be programmed. the mcu continues to poll this location, comparing dq7 (dq15) and monitoring the error bit on dq5 (dq13). when the dq7 (dq15) matches data bit 7 of the original data, and the error bit at dq5 (dq13) remains ?0?, then the embedded algorithm is complete. if the error bit at dq5 is ?1?, the mcu should test dq7 (dq15) again since dq7 (dq15) may have changed simultaneously with dq5 (dq13) (see figure 6 ). the error bit at dq5 (d q13) will be set if either an inte rnal timeout occurred while the embedded algorithm attempted to program the location or if the mcu attempted to program a ?1? to a bit that was not erased (not erased is logic ?0?). obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v memory blocks delailed operation doc id 7838 rev 2 37/104 it is suggested (as with all flash memories) to read the location again after the embedded programming algorithm has completed to compare the word that was written to flash with the word that was intended to be written. when using the data polling method after an erase instruction, figure 6 still applies. however, dq7 (dq15) will be ?0? until the erase operation is complete. a ?1? on dq5 (dq13) will indicate a timeout failure of the er ase operation, a ?0? indicates no error. the mcu can read any location within the sector being erased to get dq7 (dq15) and dq5 (dq13) . psdsoft generates ansi c code functions wh ich implement these da ta polling algorithms. figure 6. data polling flowchart read dq5 and dq7 (dq13 and dq15) at valid even address start read dq7 (dq15) program or erase cycle failed program or erase cycle is complete ai04920 yes no yes no dq5 (dq13) = 1 dq7 (dq15) = data7 (data15) yes no issue reset instruction dq7 (dq15) = data7 (data15) obsolete product(s) - obsolete product(s)
memory blocks delailed operation psd4135g2, psd4135g2v 38/104 doc id 7838 rev 2 data toggle checking the data toggle bit on dq6 (dq14) is a method of determining whether a program or erase instruction is in progress or has completed. figure 7 shows the data toggle algorithm. when the mcu issues a programming instruction, the embedded algorithm within the psd4135g2g2v begins. the mcu then reads the location to be programmed in flash to check status. data bit dq6 (dq14) of this loca tion will toggle each time the mcu reads this location until the embedded algorithm is complete. the mcu continues to read this location, checking dq6 (dq14) and monitoring the error bit on dq5 (dq13) . when dq6 (dq14) stops toggling (two consecutive reads yield the same value), and the error bit on dq5 (dq13) remains ?0?, then the embedded algorithm is complete. if the error bit on dq5 (dq13) is ?1?, the mcu should test dq6 (dq14) again, since dq6 (dq14) may have changed simultaneously with dq5 (dq13) (see figure 7 ). the error bit at dq5 (d q13) will be set if either an inte rnal timeout occurred while the embedded algorithm attempted to program, or if the mcu attempted to program a ?1? to a bit that was not erased (not erased is logic ?0?). it is suggested (as with all flash memories) to read the location again after the embedded programming algorithm has completed to compare the word that was written to flash with the word that was intended to be written. when using the data toggle method after an erase instructin, figure 7 still applies. dq6 (dq14) will toggle until the erase operation is complete. a ?1? on dq5 (dq13) will indicate a timeout failure of the erase operation, a ?0? indicates no error. the mcu can read any even location within the sector being erased to get dq6 (dq14) and dq5 (dq13) . psdsoft generates ansi c code functions which implement these data toggling algorithms. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v memory blocks delailed operation doc id 7838 rev 2 39/104 figure 7. data toggle flowchart 7.1.7 unlock bypass the unlock bypass feature allows the system to program words to the flash memories faster than using the standard program instruction. th e unlock bypass instru ction is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h (see ta b l e 2 2 ). the flash memory then enters the unlock bypass mode. a two-cycle unlock bypass program instruction is all that is required to program in this mode. the first cycle in this instruction contains the unlock bypass programm command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program instruction, resulting in faster total programming time. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset instructions are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset instruction. the first cycle must contain the start read dq6 (dq14) ai04921 no no yes yes no yes program or erase cycle failed program or erase cycle is complete issue reset instruction read dq5 and dq6 (dq13 and dq14) at valid even address dq5 (dq13) = 1 dq6 (dq14) = toggle dq6 (dq14) = toggle obsolete product(s) - obsolete product(s)
memory blocks delailed operation psd4135g2, psd4135g2v 40/104 doc id 7838 rev 2 data 90h; the second cycle the data 00h. addresses are don?t care for both cycles. the flash memory then returns to reading array data mode. 7.1.8 erasing flash memory flash bulk erase the flash bulk erase instruction uses six write operations followed by a read operation of the status register, as described in ta bl e 2 2 . if any byte of the bulk erase instruction is wrong, the bulk erase instruction aborts and the device is reset to the read flash memory status. during a bulk erase, the memory status may be checked by reading status bits dq5, dq6, and dq7 (dq13, dq14, dq15), as detailed in section 7.1.6: programming flash memory . the error bit (returns a ?1? if there has been an erase failure (maximum number of erase cycles have been executed). it is not necessary to program the arra y with 00h because the psd4135g2/g2v will automatically do this before erasing to 0ffh. during execution of the bulk erase instru ction, the flash memo ry will not accept any instructions. flash sector erase the sector erase instruction uses six write operations, as described in ta bl e 2 2 . additional flash sector erase confirm commands and flash sector addresses can be written subsequently to erase other flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the timeout period of about 100 s. the input of a new sector erase inst ruction will restart the timeout period. the status of the internal timer can be monitored through the level of dq3 (dq11) (erase timeout bit). if dq3 (dq11) is ?0?, the sector erase instruction has been received and the timeout is counting. if dq3 (dq11) is ?1?, the timeout has expired and the psd4135g2/g2v is busy erasing the flash sector(s). before and during erase timeout, any instruction other than erase suspend and erase resume will abor t the instruction and reset the device to read array mode. it is not necessary to program the flash sector with 00h as the psd4135g2/g2v will do this autom atically before erasing. during a sector erase, the memory status may be checked by reading status bits dq5, dq6, and dq7 (dq13, dq14, dq15), as detailed in section 7.1.6: programming flash memory . during execution of the erase instruction, the flash block logic accepts only reset and erase suspend instructions. erasure of one flash sector may be suspended, in order to read data from another flash sector, and then resumed. suspend sector erase when a sector erase operatio n is in progress, the erase suspend instruction will suspend the operation by writing 0b0h to any even address when an appropriate chip select (fsi or csbooti) is true. (see ta b l e 2 2 ). this allows reading of data from another flash sector after the erase operation has been suspended. erase suspend is accepted only during the flash sector erase instruction execution and defaults to read array mode. an erase suspend instruction executed du ring an erase timeout will, in addition to suspending the erase, terminate the time out. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v memory blocks delailed operation doc id 7838 rev 2 41/104 the toggle bit dq6 stops toggling when the psd4135g2/g2v internal logic is suspended. the toggle bit status must be monitored at an address within the flash sector being erased. the toggle bit will stop toggling between 0. 1 s and 15 s after the erase suspend instruction has been executed . the psd4135g2/g2v will then au tomatically be set to read flash block memory array mode. if an erase suspend instruction was executed, the following rules apply: attempting to read from a fl ash sector that was being eras ed will output invalid data. reading from a flash sector that was not being erased is valid. the flash memory cannot be programmed, and will only respond to erase resume and reset instructions (read is an operation and is ok). if a reset instruction is received, data in the flash sector that was being erased will be invalid. resume sector erase if an erase suspend instruction was previously executed, the erase operation may be resumed by this instruction. the erase resume instruction consists of writing 030h to any even address while an appropriate chip select (fsi or csbooti) is true (see ta b l e 2 2 ) 7.1.9 specific features primary and secondary flash sector protect each sector of primary flash and secondary flash memory can be separately protected against program and erase functions. sector protection provides additional data security because it disables all program or erase operations. this mode can be activated (or deactivated) through the jtag-isp port or a device programmer. sector protection can be selected for each sector using the psdsoft program. this will automatically protect selected sectors when the device is programmed through the jtag port or a device programmer. flash sectors can be unprotected to allow updating of their contents using the jtag port or a device programmer. the microcontroller can read (but cannot change) the sector protection bits. any attempt to program or erase a protecte d flash sector will be ig nored by the device. the verify operation will result in a read of the protected data. this allo ws a guarantee of the retention of the protection status. the sector protection status can either be read by the mcu through the flash protection and secondary flash protection registers (csi op), or use the read sector protection instruction (see ta b l e 2 2 ). 7.1.10 reset the reset instruction consists of one write cycle (see ta bl e 2 2 ). it can also be optionally preceded by the standard two write decoding cycles (writing aah to aaah and 55h to 554h). the reset instruction must be executed after: reading the flash protection status or flash id using the flash instruction. when an error condition occurs (dq5 (dq13) goes high) during a flash programming or erase cycle. obsolete product(s) - obsolete product(s)
memory blocks delailed operation psd4135g2, psd4135g2v 42/104 doc id 7838 rev 2 the reset instruction will reset the flash to normal read mode immediately. however, if there is an error cond ition (dq5 (dq13) goes high), the flash memory will return to the read mode in 25 s after th e reset instruction is issued. the reset instruction is ignored when it is i ssued during a flash programming or bulk erase cycle. the reset instruction will abort the on go ing sector erase cycle and return the flash memory to normal read mode in 25 s. 7.1.11 reset (reset ) pin input the reset pulse input from the pin will abort any operation in progress and reset the flash memory to read mode. when the reset occurs during a programming or erase cycle, the flash memory will take up to 25 s to return to read mode. it is reco mmended that the reset pulse (except power-on reset, see section 7.1.10: reset ) be at least 25 seconds such that the flash memory will always be ready for th e mcu to fetch the boot code after reset is over. 7.2 sram the sram is enabled when rs0?the sram chip select output from the dpld?is high. rs0 can contain up to three product terms, allowing flexible memory mapping. the chip select signal (rs0) for the sram is configured using psdsoft. 7.3 memory select signals the primary flash (fsi), secondary flash (csbooti), and sram (rs0) memory select signals are all outputs of the dpld. they are defined using psdsoft. the following rules apply to the equations for the internal chip select signals: primary flash memory and secondary flash memory sector select signals must not be larger than the physical sector size. any primary flash memory sector must not be mapped in the same memory space as another primary flash sector. a secondary flash memory sector must not be mapped in the same memory space as another flash boot sector. sram and i/o spaces must not overlap. a secondary flash memory sector may overlap a primary flash memory sector. in case of overlap, priority will be given to the flash boot sector. sram, i/o, and peripheral i/o spaces may overlap any other memory sector. priority will be given to the sram, and i/o. example fs0 is valid when the address is in the range of 8000h to bfffh, csboot0 is valid from 8000h to 9fffh, and rs0 is valid from 8000h to 87ffh. any address in the range of rs0 will always access the sram. any address in the range of csboot0 greater than 87ffh (and less than 9fffh) will aut omatically address boot memo ry segment 0. any address greater than 9fffh will access th e flash memory segment 0. you can see that half of the flash memory segment 0 and one-fourth of boot segment 0 can not be accessed in this obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v memory blocks delailed operation doc id 7838 rev 2 43/104 example. also note that an equation that defined fs1 to anywhere in the range of 8000h to bfffh would not be valid. figure 8 shows the priority levels for all memory components. any component on a higher level can overlap and has priority over any component on a lower level. components on the same level must not overlap. level one has the highest priority and level 3 has the lowest. figure 8. priority level of memory and i/o components 7.3.1 memory select confi guration for mcus with separate program and data spaces the 80c51xa and compatible family of microcontrollers, can be configured to have separate address spaces for c ode memory (selected using psen ) and data memory (selected using rd ). any of the memories within the psd4135g2/g2v can reside in either space or both spaces. this is controlled through manipulation of the vm register that resides in the psd?s csiop space. the vm register is set using psdsoft to have an initial value. it can subsequently be changed by the microcontroller so that memory mapping can be changed on-the-fly. for example, you may wish to have sram and primary flash in data space at boot, and secondary flash memory in program space at boot, and later swap main and secondary flash memory. this is easily done with the vm register by using psdsoft to configure it for boot up and having the microcontroller change it when desired. ta bl e 1 8 describes the vm register. 7.3.2 configuration modes for mcus with separate prog ram and data spaces separate space modes code memory space is separated from data memory space. for example, the psen signal is used to access the program code from the primary flash memory, while the rd signal is used to access data from the secondary flash memory, sram and i/o ports. this configuration requires the vm register to be set to 0ch. combined space modes the program and data memory spaces are combined into one space that allows the main flash memory, secondary flash memory, and sram to be accessed by either psen or rd . for example, to configure the primary flash memory in combined space mode, bits 2 and 4 of the vm register are set to ?1?. level 1 sram, i /o, or peripheral i /o level 2 secondary non-volatile memory highest priority lowest priority level 3 primary flash memory ai02867d obsolete product(s) - obsolete product(s)
memory blocks delailed operation psd4135g2, psd4135g2v 44/104 doc id 7838 rev 2 80c51xa memory map example see application notes for examples. figure 9. 80c51xa memory modules - separate space figure 10. 80c51xa memory modules - combined space 7.4 page register the eight bit page register increases the addr essing capability of the microcontroller by a factor of up to 256. the contents of the register can also be read by the microcontroller. the outputs of the page register (pgr0-pgr7) are inputs to the pld decoder and can be included in the flash memory, secondary flash memory, and sram chip select equations. primary flash memory dpld secondary flash memory sram rs0 csboot0-3 fs0-fs7 cs cs cs oe oe rd psen oe ai02869c primary flash memory dpld secondary flash memory sram rs0 csboot0-3 fs0-fs7 rd cs cs cs rd oe oe vm reg bit 2 psen vm reg bit 0 vm reg bit 1 vm reg bit 3 vm reg bit 4 oe ai02870c obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v memory blocks delailed operation doc id 7838 rev 2 45/104 if memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the pld for general logic. see application notes. figure 11 shows the page register. the eight flip flops in the register are connected to the internal data bus. the microcontroller can write to or read from the page register. the page register can be accessed at address location csiop + e0h. figure 11. page register 7.5 memory id registers the 8-bit read only memory status registers are included in the csiop space. the user can determine the memory configuration of the psd device by reading the memory id0 and memory id1 registers. the content of the registers is defined as shown in ta b l e 1 9 and ta bl e 2 0 . reset d0-d7 r/w d0 q0 q1 q2 q3 q4 q5 q6 q7 d1 d2 d3 d4 d5 d6 d7 page register pgr0 pgr1 pgr2 pgr3 dpld and cpld internal selects and logic pld pgr4 pgr5 pgr6 pgr7 ai02871b obsolete product(s) - obsolete product(s)
plds psd4135g2, psd4135g2v 46/104 doc id 7838 rev 2 8 plds the plds bring programmable logic functionality to the psd4135g2/g2v. after specifying the logic for the plds in psdsoft, the logic is programmed into the device and available upon power-up. the psd4135g2 and psd4135g2v contain two plds: the decode pld (dpld), and the general purpose pld (gpld). the plds are briefly discussed in the next few paragraphs, and in more detail in section 8.1: decode pld (dpld) and section 8.2: general purpose pld (gpld) . figure 11 shows the configuration of the plds. the dpld performs address decoding for internal components, such as memory, registers, and i/o port selects. the gpld can be used to generate external chip selects, control signals or logic functions. the gpld has 24 outputs that are connected to port a, b and c. the and array is used to form product terms. these product terms are specified using psdsoft. an input bus consisting of 66 signals is connected to the plds. the signals are shown in ta b l e 2 5 . the complement of the 66 signals are also available as inputs to the and array. psd turbo bit the plds in the psd4135g2/g2v can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70 ns. setting the turbo mode bit to off (bit 3 of the pmmr0 re gister) automatically places the plds into standby if no inputs are changing. turbo-off mode increases propagation delays while reducing power consumption. refer to the section 3.9: power management unit (pmu) on how to set the turbo bit. additionally, five bits are available in the pmmr2 register to block mcu control signals from entering the plds. this reduces power consumption and can be used only when these mcu control signals are not used in pld logic equations. table 25. dpld and gpld inputs input source input name number of signals mcu address bus (1) 1. the address inputs are a19-a4 in 80c51xa mode. a15-a0 16 mcu control signals cntl0-cntl2 3 reset rst 1 power-down pdn 1 port a input macrocells pa7-pa0 8 port b input macrocells pb7-pb0 8 port c input macrocells pc7-pc0 8 port d inputs pd3-pd0 4 port f inputs pf7-pf0 8 page register pgr7-pgr0 8 flash memory program status bit ready/busy 1 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v plds doc id 7838 rev 2 47/104 figure 12. pld block diagram pld input bus 8 csiop select sram select flash boot memory selects decode pld page register gpld general purpose pld flash memory selects data bus 8 pld out port a port b port c pld out pld out port a pld input port b pld input port c pld input port d pld input port f pld input 4 1 1 8 8 8 8 4 8 8 8 66 66 port d port f obsolete product(s) - obsolete product(s)
plds psd4135g2, psd4135g2v 48/104 doc id 7838 rev 2 8.1 decode pld (dpld) the dpld, shown in figure 11 , is used for decoding the address for internal components. the dpld can generate the following decode signals: 8 sector selects for the primary flash memory (three product terms each) 4 sector selects for the secondary flash memory (three product terms each) 1 internal sram select (three product terms) 1 internal csiop select (select psd registers, one product term) inputs to the dpld chip selects may include address inputs, page register inputs and other user defined external inputs from ports a, b, c, d or f. figure 13. dpld logic array 1. * the address inputs are a[19:4] in 80c51xa mode. 2. additional address lines can be brought in to psd via port a, b, c, c or f. (inputs) (32) (16) (1) pdn (apd output) i /o ports (port a,b,c,f) (8) pgr0 - pgr7 a [ 15:0 ] * (4) (3) pd [ 3:0 ] (ale,clkin,csi) cntrl [ 2:0 ] ( read/write control signals) (1) (1) reset rd_bsy rs0 csiop 8 flash memory sector selects 4 secondary flash memory sector selects sram select i/o decoder select csboot 0 csboot 1 csboot 2 csboot 3 fs0 fs7 3 3 3 3 3 3 3 3 3 3 3 3 3 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v plds doc id 7838 rev 2 49/104 8.2 general purpose pld (gpld) the general purpose pld implements user defined system combinatorial logic function or chip selects for external devices. figure 14 shows how the gpld is connected to the i/o ports. the gpld has 24 outputs and each are routed to a port pin. the port pin can also be configured as input to the gpld. when it is not used as gpld output or input, the pin can be configured to perform other i/o functions. all gpld outputs are identical except in the number of available product terms (pts) for logic implementation. select the pin that can best meet the pt requirement of your logic function or chip select. in general, a pt is consumed for each logic ?or? function that you specify in psdsoft. however, certain logic functions can consume more than one pt even if no logic ?or? is specified (such as specifyi ng an address range with boundaries of high granularity). ta bl e 2 6 shows the number of ?native? pts for each gpld output pin. a native pt means that a particular pt is dedicated to an output pin. for example, ta b l e 2 6 shows that psd port a pin pa0 has 3 native product terms. this means a guaranteed minimum of 3 pts is available to implement logic for that pin. psd silicon and psdsoft can in clude additional pts beyong th e native pts to implement logic. this is a transparent operation that occurs as needed through pt expansion (internal feedback) or pt allocation (internal borrowing). you may notice in the fitter report generated by psdsoft that for a given gpld output pin, more pts were used to implement logic than the number of native pts available for that pin. this is because psdsoft has called on unused pts from other gpld output pins to make your logic design fit (pt allocation or pt expansion). for optimum results, choose a gpld output pin with a large number of native pts for complicated logic. table 26. gpld product term availability gpld output on port pin number of native product terms port a, pins pa0-3 3 port a, pins pa4-7 9 port b, pins pb0-3 4 4 port b, pins pb4-7 7 7 port c, pins pc0-7 1 obsolete product(s) - obsolete product(s)
plds psd4135g2, psd4135g2v 50/104 doc id 7838 rev 2 figure 14. the microcell and i/o port product term pin pa0-3 has 3 native pts pin pa4-7 has 9 native pts polarity select other i/o function other i/o function other i/o function general purpose pld (gpld) i/o port pld input bus mux pld input pld input pld input and array port a product term pin pb0-3 has 4 native pts pin pb4-7 has 7 native pts polarity select pld output pld output mux and array port b product term pin pc0-7 has 1 native pt polarity select pld output mux and array port c * * * obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v mcu bus interface doc id 7838 rev 2 51/104 9 mcu bus interface the ?no-glue logic? psd4135g2/g2v microcon troller bus interface can be directly connected to most popular microcontrollers and their control signals. key 16-bit microcontrollers with their bus types and control signals are shown in ta bl e 2 7 . the mcu interface type is spec ified using the psdsoft. table 27. mcus and their control signals mcu cntl0 cntl1 cntl2 pd3 pd0 (1) 1. ale/as input is optional for mcus with a non-multiplexed bus adio0 pf3- pf0 68302, 68306, mmc2001 r/w lds uds (2) 2. unused cntl2 pin can be configured as pld input. other unused pins (pd3-pd0, pf3-pf0) can be con- figured for other i/o functions. as ? (2) 68330, 68331, 68332, 68340 r/w ds siz0 (2) as a0 (2) 68lc302, mmc2001 wel oe ?weh as ? (2) 68hc16 r/w ds siz0 (2) as a0 (2) 68hc912 r/w elstrb dbe ea0 (2) 68hc812 (3) 3. this configuration is fo r 68c812a4_ec at 5mhz, 3v only. r/w elstrb (2) (2) a0 (2) 80196 wr rd bhe (2) ale a0 (2) 80196sp wrl rd (2) wrh ale a0 (2) 80186 wr rd bhe (2) ale a0 (2) 80c161, 80c164-80c167 wr rd bhe (2) ale a0 (2) 80c51xa wrl rd psen wrh ale a4/d0 a3-a1 h8/300 wrl rd (2) wrh as a0 ? m37702m2 r/w ebhe (2) ale a0 (2) obsolete product(s) - obsolete product(s)
mcu bus interface psd4135g2, psd4135g2v 52/104 doc id 7838 rev 2 9.1 psd interface to a multiplexed bus figure 19 shows an example of a system using a microcontroller with a 16-bit multiplexed bus and a psd4135g2/g2v. the adio port on the psd4135g2/g2v is connected directly to the microcontroller address/data bus. ale la tches the address lines internally. latched addresses can be brought out to port e, f or g. the psd4135g2 and psd4135g2v drive the adio data bus only when one of its internal resources is accessed and the rd input is active. should the system address bus exceed sixteen bits, ports a, b, c, or f may be used as additional address inputs. figure 15. an example of a typical 16-bit multiplexed bus interface mcu wr rd bhe ale reset ad [ 7:0 ] ad[15:8] a [ 15: 8 ] a [ 7: 0 ] adio port port f port g port a wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d ( optional ) ( optional ) psd ai04928b a [ 23:16 ] ( optional ) obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v mcu bus interface doc id 7838 rev 2 53/104 9.2 psd interface to a non-multiplexed bus figure 20: interfacing a psd4135g2 with a h83/2350 shows an example of a system using a microcontroller with a 16-bit non-multiplexed bus and a psd4135g2/g2v. the address bus is connected to the adio port, and the data bus is connected to port f and g. port f and g are in tri-state mode when the psd4135g2g2v is not accessed by the microcontroller. should the system address bus exceed sixteen bits, ports a, b or c may be used for additional address inputs. figure 16. an example of a typical 16-bit non-multiplexed bus interface 9.3 data byte enable reference microcontrollers have different data byte orientations. the following tables show how the psd4135g2/g2v interprets byte/word operation in different bus write configurations. even- byte refers to locations with address a0 equal to zero and odd byte as locations with a0 equal to one. mcu wr rd bhe ale reset d [ 15:0 ] a [ 15:0 ] d[15:8] 1 d [ 7:0 ] adio port port f port g port a wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d psd ai04929 a [ 23:16 ] ( optional ) obsolete product(s) - obsolete product(s)
mcu bus interface psd4135g2, psd4135g2v 54/104 doc id 7838 rev 2 9.4 mcu interface examples figure 17 , figure 18 , figure 19 , and figure 20 show examples of the basic connections between the psd4135g2/g2v and some popular microcontrollers. the psd4135g2 control input pins are labeled as the microcontroller function for which they are configured. the mcu interface is sp ecified using psdsoft. 9.4.1 80c196 and 80c186 in figure 17 , the intel 80c196 microcontroller, which has a multiplexed sixteen-bit bus, is shown connected to a psd4135g2. the wr and rd signals are connected to the cntl0-1 pins. the bhe signal is used for high data byte selection. if bhe is not used, the psd can be configured to receive the wrl and wrh from the mcu. higher address inputs (a16- a19) can be routed to port a, b or c as inputs to the pld. the amd 80186 family has the same bus connection to the psd as the 80c196.mc683xx and 68hc16 figure 18 shows a motorola mc68331 with non-multiplexed sixteen-bit data bus and 24-bit address bus. the data bus from the mc68331 is connected to port f (d0-7) and port g (d8- d15). the siz0 and a0 inputs determine the high/low byte selection. the r/w , ds and siz0 are connected to the cntl0-2 pins. the 68hc16 and other members of the 683xx family have the same connection as the 68331 shown in figure 18 . table 28. 16-bit data bus with bhe bhe a0 d15-d8 d7-d0 0 0 odd byte even byte 0 1 odd byte ? 10? even byte table 29. 16-bit data bus with wrh and wrl wrh wrl d15-d8 d7-d0 0 0 odd byte even byte 0 1 odd byte ? 10? even byte table 30. 16-bit data bus with siz0, a0 (motorola mcu) siz0 a0 d15-d8 d7-d0 0 0 even byte odd byte 1 0 even byte ? 1 1 ? odd byte obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v mcu bus interface doc id 7838 rev 2 55/104 figure 17. interfacing the psd4135g2 with an 80c196 table 31. 16-bit data bus with lds , uds (motorola mcu) lds uds d15-d8 d7-d0 0 0 even byte odd byte 1 0 even byte ? 0 1 ? odd byte gnd 8 reset 30 49 50 70 p s d41 3 5g2 v cc 92969 v cc v cc v cc gnd gnd gnd gnd a[19:16] a[19:16] ad[15:0] ad[15:0] v cc 8 0c196nt a16 a17 a18 a19 p3.0/ad0 p3.1/ad1 p3.2/ad2 p3.3/ad3 p3.4/ad4 p3.5/ad5 p3.6/ad6 p3.7/ad7 p4.0/ad8 p4.1/ad9 p4.2/ad10 p4.3/ad11 p4.4/ad12 p4.5/ad13 p4.6/ad14 p4.7/ad15 ep.0/a16 ep.1/a17 ep.2/a18 ep.3/a19 wr/wrl/p5.2 rd/p5.3 bhe/wrh/p5.5 ale/adv/p5.0 reset ready/p5.6 ea buswidth/p5.7 inst/p5.1 slpint/p5.4 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 7 8 4 31 2 33 10 3 1 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 x1 x2 nmi p6.0/epa8 p6.1epa9 p6.2/t1clk p6.3/t1dir ach4/p0.4/pmd.0 ach5/p0.5/pmd.1 ach6/p0.6/pmd.2 ach7/p0.7/pmd.3 p2.0/tx/pvr p2.1/rxd/pale p2.2/exint/prog p2.3/intb p2.4/intintout p2.5/hld p2.6/hlda/cpver p2.7/clkout/pac p6.4/sc0 p6.5/6d0 p6.6/sc1 p6.7/sd1 vref vpp angnd p1.7/epa7 p1.0/epaq/t2clk p1.1/epa1 p1.2/epa2/t2dir p1.3/epa3 p1.4/epa4 p1.5/epa5 p1.6/epa6 67 66 32 58 59 60 61 44 45 46 47 36 37 38 39 40 41 42 43 62 63 54 65 49 6 48 50 57 56 55 54 53 52 51 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 adio8 adi09 adio10 adio11 adio12 adio13 adio14 adio15 crtl0 (wr) cntl1 (rd) cntl2 (bhe) pdo (ale) pd1 (clkin) pd2 (csi) pd3 (wrh) reset peo (tms) pe1 (tck/st) pe2 (tdi) pd2 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 pe7 u3 c ryata l reset ale bhe rd wr a16 a17 a18 a19 obsolete product(s) - obsolete product(s)
mcu bus interface psd4135g2, psd4135g2v 56/104 doc id 7838 rev 2 9.4.2 mc683xx and 68hc16 figure 18 shows a motorola mc68331 with non-multiplexed sixteen-bit data bus and 24-bit address bus. the data bus from the mc68331 is connected to port f (d0-7) and port g (d8- d15). the siz0 and a0 inputs determine the high/low byte selection. the r/w , ds and siz0 are connected to the cntl0-2 pins. the 68hc16 and other members of the 683xx family have the same connection as the 68331 shown in figure 18 . figure 18. interfacing the psd with an mc68331 gnd 8 reset reset 30 49 50 70 p s d41 3 5g2 v cc 92969 v cc v cc v cc gnd gnd gnd gnd d[15:0] d[15:0] a[23:0] a[23:0] mc6 833 1 (siz0) a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19_cs6 a20_cs7 a21_cs8 a22_cs9 a23_cs10 r_w ds siz0 as reset siz1 clkout csboot br_cso bg_cs1 bgack_cs2 fco_cs3 fc1_cs4 fc2_cs5 90 20 21 22 23 24 25 26 27 30 31 32 33 35 36 37 38 41 42 121 122 123 124 125 79 85 111 110 109 108 105 104 103 102 89 88 77 76 75 74 73 72 71 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a16 a17 a18 a19 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 crtl0 (r/w) cntl1 (ds) cntl2 pd0 (as) pd1 (clkin) pd2 (csi) pd3 reset pe0 (tms) pe1 (tck/st) pe2 (tdi) pd3 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 pe7 dsack0 dsack1 irq1 irq2 irq3 irq4 irq5 irq6 irq7 100 99 98 97 94 93 92 91 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 81 82 68 80 66 112 113 114 115 118 119 120 r/w ds as siz0 reset a16 a17 a18 a19 a20 a21 a22 a23 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v mcu bus interface doc id 7838 rev 2 57/104 9.4.3 80c51xa the philips 80c51xa microcon troller has a 16-bit multiplexed bus with burst cycles. address bits a[3:1] are not multiplexed while a[19:4] are multiplexed with data bits d[15:0]. the psd4135g2 supports the 80c51xa burst mode. the wrh signal is connected to the pd3 and the wrl is connected to cntl0 pin. the rd and psen signal is connected to cntl1-2 pins. figure 19 shows the xa schematic. the 80c51xa improves bus throughput and performance by issuing burst cycles to fetch codes from memory. in burst cycles, addresses a19-4 are latched internally by the psd, while the 80c51xa drives the a3-1 lines to sequentially fetch up to 16 bytes of code. the psd access time is then measured from address a3-a1 valid to data in valid. the psd bus timing requirement in burst cycle is identical to the normal bus cycle except the address set up or hold time with respect to ale is not required. obsolete product(s) - obsolete product(s)
mcu bus interface psd4135g2, psd4135g2v 58/104 doc id 7838 rev 2 figure 19. interfacing the psd with an 80c51xa-g3 gnd 8 reset reset 30 49 50 70 p s d41 3 5g2 xa-g 3 v cc 9 a1 a2 a3 29 69 v cc v cc v cc gnd gnd gnd gnd d[15:0] d[15:0] a[3:1] a[3:1] v cc a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d8 a13d9 a14d10 a15d11 a16d12 a17d13 a18d14 a19d15 a3 a2 a1 a0/wrh wrl rd psen ale 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 5 4 3 2 18 19 32 33 21 20 11 13 6 7 9 8 10 10 14 15 35 17 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d8 a13d9 a14d10 a15d11 a16d12 a17d13 a18d14 a19d15 xtal1 xtal2 rxd0 txd0 rxd1 txd1 t2ex t2 t0 rst int0 int1 ea/wait busw adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 adio8 adi09 adio10 adio11 adio12 adio13 adio14 adio15 crtl0 (wr) cntl1 (rd) cntl2 pd0 (ale) pd1 (clkin) pd2 (csi) pd3 (wrh) reset peo (tms) pe1 (tck/st) pe2 (tdi) pd3 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 pe7 c ryata l wrl rd psen ale a3 a2 a1 wrh obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v mcu bus interface doc id 7838 rev 2 59/104 9.4.4 h8/300 figure 20 shows a hitachi h8/2350 with non-multiplexed sixteen-bit data bus and 24-bit address bus. the h8 data bus is connected to port f (d0-7) and port g (d8-15). the wrl , wrh and rd signals are connected to the cntl0, pd3 and cntl1 pins respectively. the as connection is optional and is required if the address are to be latched. figure 20. interfacing a psd4135g2 with a h83/2350 gnd 8 reset reset 30 49 50 70 p s d41 3 5g2 v cc 92969 v cc v cc v cc gnd gnd gnd gnd d[15:0] d[15:0] a[23:0] a[23:0] h 8 5/2 3 50 pc0/a0 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pc6/a6 pc7/a7 pb0/a8 pb1/a9 pb2/a10 pb3/a11 pb4/a12 pb5/a13 pb6/a14 pb7/a15 pa0/a16 pa1/a17 pa2/a18 pb3/a19 pa4/a20/irq4 pa5/a21/irq5 pa6/a22/irq6 pa7/a23/1rq7 lwr rd 2 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 25 26 27 28 85 83 84 73 72 75 112 111 110 109 108 107 106 105 95 96 97 98 99 100 101 102 92 116 117 118 119 120 34 35 36 37 39 40 41 42 29 30 31 32 55 53 57 56 54 58 90 89 91 88 87 86 74 71 70 69 68 67 66 65 64 60 61 62 63 113 114 115 80 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 pe0/d0 pe0/d1 pe0/d2 pe0/d3 pe0/d4 pe0/d5 pe0/d6 pe0/d7 pd0/d8 pd1/d9 pd2/d10 pd3/d11 pd4/d12 pd5/d13 pd6/d14 pd7/d15 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a16 a17 a18 a19 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 crtl0 (wrl) cntl1 (rd) cntl2 pdo (as) pd1 (clkin) pd2 (csi) pd3 (wrh) reset pe0 (tms) pe1 (tck/st) pe2 (tdi) pd3 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 pe7 cs7/irq3 cs6/irq2 irq1 irq0 rxd0 txd0 sck0 pxd1 txd1 sck1 rxd2 txd2 sck2 pf0/breq pf1/ba ck pf2/lcas/wait/b nmi po0/tioca3 po1/tiocb3 po2/tioc3/tmri po3/tiocd3/tmci po4/tioca4/tmri po5/tiob4/tmrc po6/ti0c5/tmro po7/tiocb5/tmro dreq/cs4 tend0/cs5 dreq1 tend1 mod0 mod1 mod2 pf0/phi0 as hwr reset wdtovf stby po8/tioca0/dack po9/tiocb0/dack po10/tiocc0/tcl po11/tiocd0/tcl po12/tioca1 po13/tiocb1/tcl po14/tioca2 po15/tiocb2/tcl an0 an1 an2 an3 an4 an5 an6/da0 an7/da1 adtrg pg0/cas/oe pg1/cs3 pg2/cs2 pg3/cs1 pg4/cs0 extal xtal u3 c ryata l 43 44 45 46 48 49 50 51 82 wrl d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 78 77 a16 a17 a18 a19 a20 a21 a22 a23 rd as wrh reset obsolete product(s) - obsolete product(s)
mcu bus interface psd4135g2, psd4135g2v 60/104 doc id 7838 rev 2 9.4.5 mmc2001 the motorola mcore mmc2001 microcontroller has a mod input pin that selects internal or external boot rom. the psd4135g2 can be configured as the external flash boot rom or as extension to the internal rom. the mmc2001 has a 16-bit external data bus and 20 address lines with external chip select signals. the chip select control registers allow the user to customize the bus interface and timing to fit the individual system requirem ent. a typical interface configuration to the psd4135g2 is shown in figure 21 . the mmc2001?s r/w signal is connected to the cntl0 pin, while eb0 and eb1 (enable byte0 and byte1) are connected to the cntl1 (uds ) and cntl2 (lds ) pins. the wen bit in the chip select control register should set to 1 to terminate the eb[0:1] earlier to provide the write data hold time for the psd. the wsc and wws bits in the control register are set to wait states that meet the psd access time requirement. another option is to configure the eb0 and eb1 as wrl and wrh signals. in this case the psd4135g2 control setting will be: oe , wrl , wrh where oe is the read signal from the mmc2001. figure 21. interfacing a psd4135g2 with a mmc2001 gnd 8 reset reset 30 49 50 70 u2 v cc 92969 v cc v cc v cc gnd gnd gnd gnd d[15:0] d[15:0] a[21:0] a[21:0] ui p s d41 3 5g2 mmc2001 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr17 addr18 addr19 addr20 addr21 42 43 44 45 50 51 52 53 54 56 57 60 61 62 63 64 65 66 69 70 71 72 73 74 82 81 75 76 79 80 113 114 115 116 117 118 119 120 103 104 105 106 107 108 109 112 92 91 90 78 77 68 67 58 59 36 37 26 27 19 20 55 21 12 46 47 48 22 23 24 25 28 29 30 31 129 130 131 132 121 124 125 126 128 139 140 141 142 143 144 93 94 95 96 97 100 101 102 84 83 85 86 87 88 89 1 2 3 6 4 5 7 8 9 10 11 17 18 13 16 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 exosc xsoc data 0 data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 data 9 data10 data11 data12 data13 data14 data15 txd1/siz0 rxd1/siz1 txd0/pstat0 rxd0/pstat1 rts0/pstat2 cts0/pstat3 spi_miso spi_misi spi_en spi_clk spi_gp pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 int7 int6 int5 int4 int3 int2 int1 int0 de tdo tms td1 tck trst test if gps_out fvdd fgnd clkout clkin rstout rstin lvrstin vbatt vstby mod xvdd xgnd xgnd adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a16 * a17 a18 a19 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 crtl0 (r/w) cntl1 (lds) cntl2 (uds) pd0 (as) pd1 (clkin) pd2 (csi) pd3 reset pe0 (tms) pe1 (tck/st) pe2 (tdi) pe3 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 pe7 r/w oe eb1 eb0 cs0 cs1 cs2 cs3 row7 row6 row5 row4 row3 row2 row1 row0 col7 col6 col5 col4 col3 col2 col1 col0 qvcc qvcch qgnd cvdd cgnd avdd2 agnd2 avdd1 agnd1 dvdd1 dgmd1 dvdd0 dgnd0 qvcc qvcch qvcch qgnd not used agnd0 qgnd qvcc u3 c ryata l 32 33 34 35 38 39 40 41 135 136 r/w d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 14 15 a16 a17 a18 a19 a20 a21 lds uds cso * reset gvdd0 ggnd0 gvdd1 ggnd1 hvdd hgnd qvcch qvcc qgnd jvdd jgnd 99 98 110 111 122 123 127 133 134 137 138 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v mcu bus interface doc id 7838 rev 2 61/104 9.4.6 c16x family the psd4135g2 supports infineon?s c16x fam ily of microcontrollers (c161-c167) in both the multiplexed and non-multip lexed bus configuration. in figure 22 the c167cr is shown connected to the psd4135g2 in a multiplexed bus configuration. the control signals from the mcu are wr , rd , bhe and ale and are routed to the corresponding psd pins. the c167 has another control signal setting (rd , wrl , wrh , ale) which is also supported by the psd4135g2. figure 22. interfacing a psd4135g2 with a c167r gnd 8 reset reset 30 49 50 70 p s d41 3 5g2 v cc 92969 v cc v cc v cc v cc gnd gnd gnd gnd a[19:16] a[19:16] ad[15:0] ad[15:0] c167cr a16 a17 a18 a19 v ss 143 139 127 110 94 83 71 55 45 18 38 agnd v ss v ss v ss v ss v ss v ss v ss v ss v ss 144 136 129 109 93 82 72 56 46 17 v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 p4.0/a16 a17 a18 a19 a20 a21 a22 p4.7/a23 wr/wrl rd p312/bhe/wrh ale ea p1h7 p1h6 p1h5 p1h4 p1h3 p1h2 p1h1 p1h0 p1l7 p1l6 p1l5 p1l4 p1l3 p1l2 p1l1 p1l0 p2.0/cc0io p2.1/cc1io p2.2/cc2io p2.3/cc3io p2.4/cc4io p2.5/cc5io p2.6/cc6io p2.7/cc7io p2.8/cc8io/ex0in p2.9/cc9io/ex1in p2.10cc10io/ex2in p2.11/cc11io/ex3in p2.12/cc12io/ex4in p2.13/cc13io/ex5in p2.14/cc14io/ex6in p2.15/cc15io/ex7in rstin rstout nmi 100 101 102 103 104 105 106 107 108 111 112 113 114 115 116 117 85 86 87 88 89 90 91 92 96 95 79 98 99 135 134 133 132 131 130 129 128 125 124 123 122 121 120 119 118 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64 140 141 142 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 xtal1 xtal2 p3.0/t0in p3.1/t6out p3.2/capin p3.4/t3tout p3.4/t3eud p3.5/t4in p3.6/t3in p3.7/t2in p3.8/mrst p3.10/txd0 p3.10/txd0 p3.11/rxd0 p3.13/sclk p3.15/clkout p5.0/an0 p5.1/an1 p5.2/an2 p5.3/an3 p5.4/an4 p5.5/an5 p5.6/an6 p5.7/an7 p5.9/an8 p5.9/an9 p5.10/an10/t6ued p5.11/an11/t5ued p5.12/an12/t6in p5.14/an14/t4ued p5.15/an15/t2ued p6.0/ cso p6.1/ cs1 p6.2/ cs2 p6.3/ cs3 p6.4/ cs4 p6.5/ hold p6.6/ hlda p6.7/ breq p7.0/pout0 p7.1/pout1 p7.2/pout2 p7.3pout/3 p7.4/cc28io p7.5/cc29io p7.6/cc30io p7.7/cc31io p8.0/cc16io p8.1/cc17io p8.2/cc18io p8.3/cc19io p8.4/cc20io p8.5/cc21io p8.6/cc22io p8.7/cc23io vref ready 138 137 65 66 67 68 69 70 73 74 75 76 77 78 80 81 27 28 29 30 31 32 33 34 35 36 39 40 41 43 44 1 2 3 4 5 6 7 8 19 20 21 22 23 24 25 26 9 10 11 12 13 14 15 16 37 97 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 adio8 adi09 adio10 adio11 adio12 adio13 adio14 adio15 crtl0 (wr) cntl1 (rd) cntl2 (bhe) pdo (ale) pd1 (clkin) pd2 (csi) pd3 (wrh) reset peo (tms) pe1 (tck/st) pe2 (tdi) pd2 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 pe7 u3 c ryata l reset ale bhe rd wr a16 a17 a18 a19 obsolete product(s) - obsolete product(s)
i/o ports psd4135g2, psd4135g2v 62/104 doc id 7838 rev 2 10 i/o ports there are seven programmable i/o ports: ports a, b, c, d, e, f and g. each of the ports is eight bits except port d, which is 4 bits. each port pin is individually user configurable, thus allowing multiple functions per port. the ports are configured using psdsoft or by the microcontroller writing to on-chip registers in the csiop address space. the topics discussed in this section are: general port architecture port operating modes port configuration registers port data registers individual port functionality 10.1 general port architecture the general architecture of the i/o port is shown in figure 23 . individual port architectures are shown in figure 24 , figure 25 , and figure 26 . in general, once the purpose for a port pin has been defined, th at pin will no longer be available fo r other purposes. exceptions will be noted. as shown in figure 23 , the ports contain an output multiplexer whose selects are driven by the configuration bits in the control registers (ports e, f and g only) and psdsoft configuration. inputs to the mu ltiplexer include the following: output data from the data out register latched address outputs gpld outputs (external chip selects) the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read. the pdb is connected to the internal data bus for feedback and can be read by the microcontroller. the data out and microcell outputs, direction and control registers, and port pin input are all connected to the pdb. the contents of these registers can be alte red by the microcontroller. the pdb feedback path allows the microcontroller to check the contents of the registers. 10.2 port operating modes the i/o ports have several modes of operation. some modes can be defined using psdsoft, some by the microcontroller writing to the registers in csiop space, and some by both. the modes that can only be defined using psdsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. the modes that can be changed by the microcontroller can be done so dynamically at run-time. the pld i/o, data port, address input, and mcu reset modes are the only modes that must be defined before programming the device. all other modes can be changed by the microcontroller at run-time. ta bl e 3 2 summarizes which modes are available on each port. ta bl e 3 5 shows how and where the different modes are configured. each of the port operating modes are described in the following subsections. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v i/o ports doc id 7838 rev 2 63/104 figure 23. general i/o port architecture internal data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term ( .oe ) ext cs ale read mux p d b cpld - input control reg. dir reg. input macrocell enable out data in output select output mux port pin data out address ai02885 table 32. port operating modes port mode port a port b port c port d port e port f port g m c u i / o ye s ye s ye s ye s ye s ye s ye s pld outputs yes yes yes no no no no p l d i n p u t s ye s ye s ye s ye s n o ye s n o address out no no no no yes (a7 - 0) yes (a7 - 0) yes (a7 - 0) or (a15 - 8) address in yes yes yes yes no yes no data port no no no no no yes yes jtag isp no no no no yes no no mcu reset mode (1) no no no no no yes yes 1. available to motorola 16-bit 683xx and hc16 families of mcus. obsolete product(s) - obsolete product(s)
i/o ports psd4135g2, psd4135g2v 64/104 doc id 7838 rev 2 10.2.1 mcu i/o mode in the mcu i/o mode, the microcontroller uses the psd4135g2/g2v ports to expand its own i/o ports. by setting up the csiop space, the ports on the psd4135g2/g2v are mapped into the microcontroller address space. the addresses of the ports are listed in ta bl e 6 . a port pin can be put into mcu i/o mode by writing a ?0? to the corresponding bit in the control register (port e, f and g). the mcu i/o direction may be changed by writing to the corresponding bit in the direction register (see section 10.3.2: direction register ). when the pin is configured as an output, the content of the data out register drives the pin. when configured as an input, the microcontroller can read the port input through the data in buffer (see figure 23 ). ports a, b and c do not have control registers, and are in mcu i/o mode by default. they can be used for pld i/o if they are specified in psdsoft. 10.2.2 pld i/o mode the pld i/o mode uses a port as an input to the gpld?s input microcells, and/or as an output from the gpld. the corresponding bit in the direction register must not be set to ?1? if the pin is defined as a pld input pin in psdsoft. the pld i/o mode is specified in psdsoft by declaring the port pins, and then specifying an equation in psdsoft. 10.2.3 address in mode for microcontrollers that have more than 16 address lines, the higher addresses can beconnected to ports a, b, c, d or f and are routed as inputs to the plds. the address input can be latched by the address strobe (ale/as). any input that is included in the dpld equations for the primary flash, boot flash, or sram is considered to be an address input. table 33. port operating mode settings (1) 1. n/a = not applicable mode defined in psdsoft express control regis- ter setting direction regis- ter setting vm register setting mcu i/o declare pins only 0 (2) 2. control register setting is not applicable to ports a, b and c. 1 = output, 0 = input n/a pld i/o declare pins and logic equations n/a n/a data port (port f, g) selected for mcu with non-multiplexed bus n/a n/a n/a address out (port e, f, g) declare pins only 1 1 n/a address in (port a, b, c, d, f) declare pins n/a n/a n/a jtag isp declare pins only n/a n/a n/a mcu reset mode specific pin logic level n/a n/a n/a obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v i/o ports doc id 7838 rev 2 65/104 10.2.4 data port mode port f and g can be used as a data bus port for a microcontroller with a non-multiplexed address/data bus. the data port is connected to the data bus of the microcontroller. the general i/o functions are disabled in port f and g if the ports are configured as data port. data port mode is automatica lly configured in psd soft when a non-multiplexed bus mcu is selected. 10.2.5 jtag isp port e is jtag compliant, and can be used for in-system programming (isp). 10.2.6 mcu reset mode port f and g can be configured to operate in ?mcu reset? mode. this mode is available when psd is configured for the motorola 16-bit 683xx and hc16 family and is active only during reset. at the rising edge of the reset input, the mcu reads the logic level on the data bus d15-0 pins. the mcu then configures some of its i/o pin functions according to the logic level input on the data bus lines. two dedicated buffers are usually enabled during reset to drive the data bus lines to the desired logic level. the psd4135g2/g2v can replace the two buffers by configuring port f and g to operate in mcu reset mode. in this mode, the psd will driv e the pre-defined logic level or data pattern onto the mcu data bus when reset is active and there is no ongoing bus cycle. after reset, port f and g return to the normal data port mode. the mcu reset mode is enabled and configured in psdsoft. the user defines the logic level (data pattern) that will be driven out from port f an d g during reset. 10.2.7 address out mode for microcontrollers with a multiplexed address/data bus, address out mode can be used to drive latched addresses onto the port pins. these port pins can, in turn, drive external devices. either the output enable or the corresponding bits of both the direction register and control register must be set to a ?1? for pins to use address out mode. this must be done by the mcu at run-time. see ta bl e 3 1 for the address output pin assignments on ports e, f and f for various mcus. note: do not drive address lines with address out mode to an external memory device if it is intended for the mcu to boot from the external device. the mcu must first boot from psd memory so the direction and control register bits can be set. table 34. i/o port latched address output assignments (1) mcu port e (pe3-pe0) port e (pe7-pe4) port f (pf3-pf0) port f (pf7-pf4) port g (pg3-pg0) port g (pg7-pg4) 80c51xa n/a address a7-a4 n/a address a7-a4 address a11-a8 address a15-a12 all other mcu with multiplexed bus address a3-a0 address a7-a4 address a3-a0 address a7-a4 address a11-a8 address a15-a12 1. n/a = not applicable. obsolete product(s) - obsolete product(s)
i/o ports psd4135g2, psd4135g2v 66/104 doc id 7838 rev 2 10.3 port configuration registers (pcrs) each port has a set of pcrs used for configuration. the contents of the registers can be accessed by the microcontroller through normal read/write bus cycles at the addresses given in ta b l e 6 . the addresses in ta bl e 6 are the offsets in hex from the base of the csiop register. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 of its port. the three pcrs, shown in ta b l e 3 5 , are used for setting the port configurations. the default power-up state for each register in ta b l e 3 8 is 00h. 10.3.1 control register any bit set to ?0? in the control register sets the corresponding port pin to mcu i/o mode, and a ?1? sets it to address out mode. the default mode is mcu i/o. only ports e, f and g have an associated control register. 10.3.2 direction register the direction register controls the direction of data flow in the i/o ports. any bit set to ?1? in the direction register will cause the corresponding pin to be an output, and any bit set to ?0? will cause it to be an input. the defaul t mode for all port pins is input. figure 24 , figure 25 , and figure 26 show the port architecture diagrams for ports a/b/c and e/f/g respectively. the direction of data flow for ports a, b, c and f are controlled by the direction register. an example of a configuration for a port with the three least significant bits set to output and the remainder set to input is shown in ta b l e 3 7 . since port d only contains four pins, the direction register for port d has only the four least significant bits active. table 35. port configuration registers (pcr) register name port mcu access control e, f, g write/read direction a, b, c, d, e, f, g write/read drive select (1) 1. see table 38 for drive register bit definition. a, b, c, d, e, f, g write/read table 36. port pin direction control direction register bit port pin mode 0 input 1 output table 37. port direction assignment example bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 1 1 1 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v i/o ports doc id 7838 rev 2 67/104 10.3.3 drive select register the drive select register configures the pin driver as open drain or cmos for some port pins, and controls the slew rate for the other port pins. an external pull-up resistor should be used for pins configured as open drain. a pin can be configured as open drain if its corresponding bit in the drive select register is set to a ?1?. the default pin drive is cmos. note: the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more electrical noise. a pin operates in a high slew rate when the corresponding bit in the drive register is set to ?1?. the default rate is slow slew. ta bl e 3 8 shows the drive register for ports a, b, c, d, e, f and g. it summarizes which pins can be configured as open drain outputs and which pins the slew rate can be set for. 10.4 port data registers the port data registers, shown in ta b l e 3 9 , are used by the microcontroller to write data to or read data from the ports. ta bl e 3 9 shows the register name, the ports having each register type, and microcontroller access for each register type. the registers are described below. 10.4.1 data in port pins are connected directly to the data in buffer. in mcu i/o input mode, the pin input is read through the data in buffer. table 38. drive register pin assignment (1) 1. na = not applicable. drive register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port a open drain open drain open drain open drain open drain open drain open drain open drain port b open drain open drain open drain open drain open drain open drain open drain open drain port c slew rate slew rate slew rate slew rate slew rate slew rate slew rate slew rate port dnananana open drain open drain open drain open drain port e open drain open drain open drain open drain open drain open drain open drain open drain port f slew rate slew rate slew rate slew rate slew rate slew rate slew rate slew rate port g open drain open drain open drain open drain open drain open drain open drain open drain obsolete product(s) - obsolete product(s)
i/o ports psd4135g2, psd4135g2v 68/104 doc id 7838 rev 2 10.4.2 data out register stores output data written by the mcu in the mcu i/o output mode. the contents of the register are driven out to the pins if the direction register or the output enable product term is set to ?1?. the contents of the register can also be read back by the microcontroller. 10.5 port a, b, and c registers ports a and b have similar functionality and structure, as shown in figure 24 . the two ports can be configured to perform one or more of the following functions: mcu i/o mode gpld output ? combinatorial pld outputs. pld input ? input to the plds. address in ? additional high address inputs may be latched by ale. open drain/slew rate ? pins pc[7:0]can be configured to fast slew rate, ? pins pa[7:0] and pb[7:0] can be configured to open drain mode. figure 24. port a, b, and c structure table 39. port data registers register name port mcu access data in a, b, c, d, e, f, g read - input on pin data out a, b, c, d, e, f, g write/read e product(s) - obsolete product(s) internal data bu s data out reg. dq dq wr wr read mux gpld output p d b pld input dir reg. data in output s elect output mux port pin data out obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v i/o ports doc id 7838 rev 2 69/104 10.6 port d ? functionality and structure port d has four i/o pins (see figure 25 ). port d can be configured to program one or more of the following functions: mcu i/o mode pld input ? direct input to pld port d pins can be configured in psdsoft as input pins for other dedicated functions: pd0 ? ale, as address strobe input pd1 ? clkin, as clock input to the pld and apd counter pd2 ? csi, as active low chip select inpu t. a high input will disable the flash/sram and csiop. pd3 ? wrh , as active low write enable (high byte) input or as dbe input from 68hc912 figure 25. port d structure 10.7 port e ? functionality and structure port e can be configured to perform one or more of the following functions (see figure 26 ): mcu i/o mode in-system programming ? jtag port can be enabled for programming/erase of the psd4135g2/g2v device (see section 12: in-cir cuit programming using the jtag-isp interface ).pins that are configured as jtag pins in psdsoft will not be available for other i/o functions. open drain ? port e pins can be configured in open drain mode latched address output ? provided latched address (a7-0) output internal data bu s data out reg. dq dq wr wr read mux p d b pld input dir reg. data in output s elect output mux port d pin data out obsolete product(s) - obsolete product(s)
i/o ports psd4135g2, psd4135g2v 70/104 doc id 7838 rev 2 10.8 port f ? functionality and structure port f can be configured to perform one or more of the following functions: mcu i/o mode pld input ? as direct input ot the pld array. address in ? additional high address inputs. direct input to the pld array. latched address out ? provide latched address out per ta b l e 4 3 . slew rate ? pins can be set up for fast slew rate. data port ? connected to d[7:0] when port f is configured as data port for a non- multiplexed bus. mcu reset mode ? for 16-bit motoro la 683xx and hc16 microcontrollers. 10.9 port g ? functionality and structure port g can be configured to perform one or more of the following functions: mcu i/o mode latched address out ? provide latched address out per ta bl e 4 3 . open drain ? pins can be configured in open drain mode data port ? connected to d[15:8] when port g is configured as data port for a non- multiplexed bus. mcu reset mode ? for 16-bit motoro la 683xx and hc16 microcontrollers figure 26. port e, f, and g structure internal data bu s data out reg. dq d g q dq dq wr wr wr addre ss ale read mux p d b control reg. dir reg. pld input (port f) i s p data in output s elect output mux port pin data out addre ss a [ 7:0 ] or a [ 15: 8 ] configuration bit obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v power management doc id 7838 rev 2 71/104 11 power management the psd4135g2 and psd4135g2v offer configurable power saving options. these options may be used individually or in combinations, as follows: all memory types in a psd (flash, second ary flash, and sram) are built with zero- power technology. in addition to using s pecial silicon design meth odology, zero-power technology puts the memories into standby mode when address/data inputs are not changing (zero dc current). as soon as a transition occurs on an input, the affected memory ?wakes up?, changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory standby mode when no inputs are changing?it happens automatically. the pld sections can also achieve standby mode when its inputs are not changing, see pmmr registers below. like the zero-power feature, the automatic power-down (apd) logic allows the psd to reduce to standby current automatically. the apd will bloc k mcu address/data signals from reaching the memories and plds. this feature is available on all psd4135g2/g2v device. the apd unit is described in more detail in section 11.1: automatic power-down (apd) unit and power-down mode . built in logic will monitor the address strobe of the mcu for activity. if there is no activity for a certain time period (mcu is asleep), the apd logic initiates power-down mode (if enabled). once in power-down mode, all address/data signals are blocked from reaching psd memories and plds, and the memories are deselected internally. this allows the memories and plds to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the mcu bus, etc.). keep in mind that any unblocked pld input signals that are changing states keeps the pld out of standby mode, but not the memories. the psd chip select input (csi) can be used to disable the internal memories, placing them in standby mode even if inputs are changing. this feature does not block any internal signals or disable the plds. this is a good alternative to using the apd logic, especially if your mcu has a chip select output. there is a slight penalty in memory access time when the csi signal makes its in itial transition from des elected to selected. the pmmr registers can be written by the mcu at run-time to manage power. all psd devices support ?blocking bits? in these registers that are set to block designated signals from reaching both plds. current consumption of the plds is directly related to the composite frequency of the changes on their inputs (see figure 30 and figure 31 ). significant power savings can be achieved by blocking signals that are not used in pld logic equations at run time. psdsoft creates a fuse map that automatically blocks the low address byte (a7-a0) or the control signals (cntl0-2, ale and wrh /dbe ) if none of these signals are used in pld logic equations. the psd4135g2 and psd4135g2v devices have a turbo bit in the pmmr0 register. this bit can be set to disable the turbo mode feature (default is turbo mode on). while turbo mode is disabled, the plds can achieve standby current when no pld inputs are changing (zero dc current). even when inputs do change, significant power can be saved at lower frequencies (ac current), compared to when turbo mode is enabled. conversely, when the turbo mode is enabled, there is a significant dc current component and the ac component is higher. obsolete product(s) - obsolete product(s)
power management psd 4135g2, psd4135g2v 72/104 doc id 7838 rev 2 11.1 automatic power-down (apd) unit and power-down mode the apd unit, shown in figure 27 , puts the psd into power-down mode by monitoring the activity of the address strobe (ale/as). if the apd unit is enabled, as soon as activity on the address strobe stops, a four bit counter starts counting. if the address strobe remains inactive for fifteen clock periods of the clkin signal, the power-down (pdn) signal becomes active, and the psd will enter into power-down mode, discussed next. 11.1.1 power-down mode by default, if you enable the psd apd unit, power-down mode is automatically enabled. the device will enter power-down mode if the address strobe (ale/as) remains inactive for fifteen clkin (pin pd1) clock periods. the following should be kept in mind when the psd is in power-down mode: if the address strobe starts pulsing again, the psd will return to normal operation. the psd will also return to normal operation if either the csi input returns low or the reset input returns high. the mcu address/data bus is blocked from all memories and plds. various signals can be blocked (prior to power-down mode) from entering the plds by setting the appropriate bits in the pmmr registers. the blocked signals include mcu control signals and the common clock (clkin). note that blocking clkin from the plds will not block clkin from the apd unit. all psd memories enter standby mode and are drawing standby current. however, the plds and i/o ports do not go into standby mode because you don?t want to have to wait for the logic and i/o to ?wake-up? before their outputs can change. see ta b l e 4 0 for power-down mode effects on psd ports. typical standby current is 50 a for 5 v parts. this standby current value assumes that there are no transitions on any pld input. table 40. effect of power-down mode on ports port function pin level mcu i/o no change pld out no change address out undefined data port tri-state peripheral i/o tri-state table 41. psd timing and standby current during power-down mode (1) 1. power-down does not affect the operation of the pld. the pld operation in this mode is based only on the turbo bit. mode pld propagation delay memory access time access recovery time to normal access typical standby current power- down normal t pd no access t lvdv i sb (2) 2. typical current consumption, see table 52 , assuming no pld inputs are changing state and the pld tur- bo bit is 0. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v power management doc id 7838 rev 2 73/104 figure 27. apd unit figure 28. enable power-down flowchart apd en pmmr0 bit 1=1 ale reset csi clkin transition detection edge detect apd counter power down (pdn) select disable bus interface secondary flash memory select primary flash memory select sram select pd clr pd disable primary and secondary flash memory and sram pld ai04939 enable apd set pmmr0 bit 1 = 1 psd in power down mode ale/as idle for 15 clkin clocks? reset yes no optional disable desired inputs to pld by setting pmmr0 bits 4 and 5 and pmmr2 bits 0 to 6. ai04940 obsolete product(s) - obsolete product(s)
power management psd 4135g2, psd4135g2v 74/104 doc id 7838 rev 2 11.1.2 other power saving options the psd4135g2 and psd4135g2v offer other reduced power saving options that are independent of the power-down mode. except for the sram standby and csi input features, they are enabled by setting bits in the pmmr0 and pmmr2 registers. zero power pld the power and speed of the plds are controlled by the turbo bit (bit 3) in the pmmr0. by setting the bit to ?1?, the turbo mode is disabled and the plds consume zero power current when the inputs are not switching for an extended time of 70 ns. the propagation delay time will be increa sed after the turbo bit is set to ?1? (turned off) when the inputs change at a composite frequency of less than 15 mhz. when the turbo bit is set to a ?0? (turned on), the plds run at full power and speed. the turbo bit affects the pld?s d.c. power, ac power, and propagation delay. refer to ac/dc spec for pld timings. note: blocking mcu control signals with pmmr2 bits can further reduce pld ac power consumption. the csi input pin pd2 of port d can be configured in psds oft as the csi input. when low, the signal selects and enables the internal flash, boot block, sram, and i/o for read or write operations involving the psd 4135g2/g2v. a high on the csi pin will disable the flash memory, boot block, and sram, and reduce the psd power consumption. however, the pld and i/o pins remain operational when csi is high. note: there may be a timing penalty when using the csi pin depending on the speed grade of the psd that you are using. see the timing parameter t slqv in the ac/dc specs. input clock the psd4135g2 and psd4135g2v provide the option to turn off the clkin input to the pld and array to save ac power consumption. during power-down mode, or, if the clkin input is not being used as part of the pld logic equation, the clock should be disabled to save ac power. the clkin will be disconnected fr om the pld and array by setting bit 4 to a ?1? in pmmr0. mcu control signals the psd4135g2 psd4135g2v provide the option to turn off the address input (a7-0) and input control signals (cntl0-2, ale, and wrh /dbe ) to the pld to save ac power consumption. these signals are inputs to the pld and array. during power-down mode, or, if any of them are not being used as part of the pld logic equation, these control signals should be disabled to save ac power. they will be disconnected from the pld and array by setting bits 0, 2, 3, 4, 5, and 6 to a ?1? in the pmmr2. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v power management doc id 7838 rev 2 75/104 11.1.3 reset and power-on requirement power-on reset upon power up the psd4135g2 and psd4135g2v require a reset pulse of t nlnh-po (minimum 1 ms) after v cc is steady. during this time period the device loads internal configurations, clears some of the registers and sets the flash into operating mode. after the rising edge of reset, the psd4135g2/g2v remains in the reset state for an additional topr (maximum 120 ns) nanoseconds before the first memory access is allowed. the psd4135g2/g2v flash memory is reset to the read array mode upon power up. the fsi and csbooti select signals along with the write strobe signal must be in the false state during power-up reset for maximum security of the data contents and to remove the possibility of data being written on the first edge of a write strobe signal. any flash memory write cycle initiation is pr evented automatically when v cc is below v lko . warm reset once the device is up and running, the device can be reset with a much shorter pulse of t nlnh (minimum 150 ns). the same t opr time is needed before the device is operational after warm reset. figure 29 shows the timing of the power-on and warm reset. figure 29. power-on and warm reset timing i/o pin, register and pld status at reset ta bl e 4 2 shows the i/o pin, register and pld status during power-on reset, warm reset and power-down mode. pld outputs are always valid during warm reset, and they are valid in power-on reset once the internal psd configuration bits are loaded. this loading of psd is completed typically long before the v cc ramps up to operating level. once the pld is active, the state of the outputs are determined by the equations specified in psdsoft. reset of flash erase and programming cycles an external reset on the reset pin will also reset the internal flash memory state machine. when the flash is in progra mming or erase mode, the reset pin will terminate the programming or erase operation and return the flash back to read mode in t nlnh-a (minimum 25 s) time. t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset obsolete product(s) - obsolete product(s)
power management psd 4135g2, psd4135g2v 76/104 doc id 7838 rev 2 table 42. status during power-on reset, warm reset and power-down mode port configuration power-on reset warm reset power-down mode mcu i/o input mode input mode unchanged pld output valid after internal psd configuration bits are loaded valid depends on inputs to pld (addresses are blocked in pd mode) address out tri-stated tri-stated not defined data port tri-stated tri-stated tri-stated pmmr0 and pmmr2 cleared to ?0? unchanged unchanged vm register (1) initialized, based on the selection in psdsoft express configuration menu initialized, based on the selection in psdsoft express configuration menu unchanged all other registers cleared to ?0? cleared to ?0? unchanged 1. the sr_code and peripheral mode bits in the vm register are always cleared to ?0? on power-on reset or warm reset. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v in-circuit programming using the jtag-isp interface doc id 7838 rev 2 77/104 12 in-circuit programming using the jtag-isp interface the jtag-isp interface on the psd4135g2/g2v can be enabled on port e (see ta bl e 4 3 ). all memory (flash and flash boot block), pld logic, and psd configuration bits may be programmed through the jtag-isc interface. a blank part can be mounted on a printed circuit board and programmed using jtag-isp. the standard jtag signals (ieee 1149.1) are tms, tck, tdi, and tdo. two additional signals, tstat and terr , are optional jtag extensions used to speed up program and erase operations. note: by default, on a blank psd (as shipped from the factory, or after erasure), four pins on port e are enabled for the basic jtag signals tms, tck, tdi, and tdo. see application note an1153 for more details on jtag in-system programming (isp). 12.1 standard jtag signals the jtag configuration bit (non-volatile) inside the psd can be set by the user in the psdsoft. once this bit is set and programmed in the psd, the jtag pins are dedicated to jtag at all times and is in compliance with ieee 1149 .1. after power up the standard jtag signals (tdi, tdo tck and tms) are inputs, waiting for a serial command from an external jtag controller device (such as flashlink or automated test equipment). when the enabling command is received from the external jtag controller, tdo becomes an output and the jtag channel is fully functional inside the psd. the same command that enables the jtag channel may optionally enable the two additional jtag pins, tstat and terr . the psd4135g2 and psd4135g2v support jtag isp commands, but not boundary scan. st?s psdsoft software tool and flashlink jtag programming cable implement these jtag- isp commands. table 43. jtag port signals port e pin jtag signals description pe0 tms mode select pe1 tck clock pe2 tdi serial data in pe3 tdo serial data out pe4 tstat status pe5 terr error flag obsolete product(s) - obsolete product(s)
in-circuit programming using the jtag-isp interface psd4135g2, psd4135g2v 78/104 doc id 7838 rev 2 12.2 jtag extensions tstat and terr are two jtag extension signals enabled by a jtag command received over the four standard jtag pins (tms, tck, tdi, and tdo). they are used to speed programming and erase functions by indicating status on psd pins instead of having to scan the status out serially using the standard jtag channel. see application note 54. terr will indicate if an error has occurred when erasing a sector or programming a byte in flash memory. this signal will go low (active) when an error condition occurs, and stay low until a special jtag command is executed or a chip reset pulse is received after an ?isc- disable? command. tstat behaves the same as the rdy/bsy signal described in section 7.1.2: ready/busy pin (pe4) . tstat will be high when the psd4135g2/g2v device is in read array mode (flash memory and boot block contents can be read). tstat will be low when flash memory programming or erase cycles are in progress, and also when data is being written to the secondary flash block. tstat and terr can be configured as open-drain type signals with a jtag command. 12.3 security and flash memories protection when the security bit is set, the device cannot be read on a device programmer or through the jtag port. when using the jtag port, only a full chip erase command is allowed. all other program/erase/verify commands are blocked. full chip erase returns the part to a non-secured blank state. the secu rity bit can be set in psdsoft. all flash memory and boot sectors can individually be sector protected against erasures. the sector protect bits can be set in psdsoft. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v initial delivery state doc id 7838 rev 2 79/104 13 initial delivery state when delivered from st, the psd device has all bits in the memory and plds set to '1.' the psd configuration register bits are set to '0.' the code, configuration, and pld logic are loaded using the programming procedure. information for programming the device is available directly from st. please contact your local sales representative. obsolete product(s) - obsolete product(s)
maximum rating psd4 135g2, psd4135g2v 80/104 doc id 7838 rev 2 14 maximum rating stressing the device above the rating listed in table 44: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the section 15: dc and ac parameters of this specification is not implie d. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 44. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 125 c t lead lead temperature during soldering (20 seconds max.) (1) 1. ipc/jedec j-std-020a 235 c v io input and output voltage (q = v oh or hi-z) ?0.6 7.0 v v cc supply voltage ?0.6 7.0 v v pp device programmer supply voltage ?0.6 14.0 v v esd electrostatic discharge voltage (human body model) (2) 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 , r2=500 ) ?2000 2000 v obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v dc and ac parameters doc id 7838 rev 2 81/104 15 dc and ac parameters these tables describe the ad and dc parameters of the psd4235g2: dc electrical specification ac timing specification ? pld timing combinatorial timing synchronous clock mode asynchronous clock mode input macrocell timing ? mcu timing read timing write timing peripheral mode timing power-down and reset timing the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. the following are issues concerning the parameters presented: in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the psd is in each mode. also, the supply po wer is considerably different if the turbo bit is 0. the ac power component gives the pld, flash memory, and sram ma/mhz specification. figure 30 show the pld ma/mhz as a function of the number of product terms (pt) used. in the pld timing parameters, add the required delay when turbo bit is 0. figure 30. pld i cc /frequency consumption - 5 v ai05739 0 10 20 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 highest composite frequency at pld inputs (mhz) icc - (ma) pt 100% pt 25% vcc = 5v turbo on (100%) turbo on (25%) turbo off turbo off obsolete product(s) - obsolete product(s)
dc and ac parameters psd4135g2, psd4135g2v 82/104 doc id 7838 rev 2 figure 31. pld i cc /frequency consumption - 3 v 0 10 20 30 40 50 60 v cc = 3v 01015 5 20 25 i cc ? (ma) turbo on (100%) turbo on (25%) turbo off turbo off highest composite frequency at pld inputs (mhz) pt 100% pt 25% ai03100 table 45. example of psd typical power calculation at v cc = 5.0v (with turbo mode on) (1) conditions highest composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % flash memory access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power-down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/176 = 25.5% turbo mode = on calculation (using typical values) i cc total = ipwrdown x %pwrdown + %normal x (i cc (ac) + i cc (dc)) obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v dc and ac parameters doc id 7838 rev 2 83/104 = ipwrdown x %pwrdown + % normal x (%flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x 2 ma/mhz x freq pld + #pt x 400 a/pt) = 50 a x 0.90 + 0.1 x (0.8 x 2.5 ma/mhz x 4 mhz + 0.15 x 1.5 ma/mhz x 4 mhz + 2 ma/mhz x 8 mhz + 45 x 0.4 ma/pt) = 45 a + 0.1 x (8 + 0.9 + 16 + 18 ma) = 45 a + 0.1 x 42.9 = 45 a + 4.29 ma = 4.34 ma 1. this is the operating power with no flash memory program or erase cycles in progress. calculation is based on i out =0 ma. table 45. example of psd typical power calculation at v cc = 5.0v (with turbo mode on) (1) conditions obsolete product(s) - obsolete product(s)
dc and ac parameters psd4135g2, psd4135g2v 84/104 doc id 7838 rev 2 table 46. example of psd typical power calculation at v cc = 5.0v (with turbo mode off) (1) conditions highest composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % flash memory access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power-down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/176 = 25.5% turbo mode = off calculation (using typical values) i cc total = ipwrdown x %pwrdown + %normal x (i cc (ac) + i cc (dc)) = ipwrdown x %pwrdown + % normal x (%flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x (from graph using freq pld)) = 50 a x 0.90 + 0.1 x (0.8 x 2.5 ma/mhz x 4 mhz + 0.15 x 1.5 ma/mhz x 4 mhz + 24 ma) = 45 a + 0.1 x (8 + 0.9 + 24) = 45 a + 0.1 x 32.9 = 45 a + 3.29 ma = 3.34 ma 1. this is the operating power with no flash memory program or erase cycles in progress. calculation is based on i out = 0 ma. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v dc and ac parameters doc id 7838 rev 2 85/104 table 47. operating conditions symbol parameter min. max. unit v cc supply voltage (psd4135g2) 4.5 5.5 v supply voltage (psd4135g2v) 3.0 3.6 v t a ambient operating temperature (industrial) ?40 85 c ambient operating temperature (commercial) 0 70 c table 48. ac signal letters for pld timings (1) letter description a address input c ceout output d input data ee input g internal wdog_on signal i interrupt input lale input n reset input or output p port signal output q output data rwr , uds , lds , ds , iord, psen inputs s chip select input tr/w input w internal pdn signal m output macrocell 1. example: t avlx = time from address valid to ale invalid. table 49. ac signal behavior symbols for pld timings letter description ttime l logic level low or ale h logic level high vvalid x no longer a valid logic level zfloat obsolete product(s) - obsolete product(s)
dc and ac parameters psd4135g2, psd4135g2v 86/104 doc id 7838 rev 2 figure 32. ac measurement i/o waveform figure 33. ac measurement load circuit table 50. ac measurement conditions (1) symbol parameter min. max. unit c l load capacitance 30 pf 1. output hi-z is defined as the poin t where data out is no longer driven. table 51. capacitance (1) symbol parameter test condition typ (2) max. unit c in input capacitance (for input pins) v in = 0v 4 6 pf c out output capacitance (for input/output pins) v out = 0v 8 12 pf c vpp capacitance (for cntl2/v pp )v pp = 0v 18 25 pf 1. sampled only, not 100% tested. 2. typical values are for t a = 25c and nominal supply voltages. 3.0v 0v test point 1.5v ai03103b device under test 2.01 v 195 c l = 30 pf (including scope and jig capacitance) ai03104b obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v dc and ac parameters doc id 7838 rev 2 87/104 figure 34. switching waveforms - key waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state ai03102 table 52. dc characteristics 5 v symbol parameter test condition (in addition to those in table 47 ) min. typ. max. unit v ih input high voltage voltage 4.5 v < v cc < 5.5 v 2 v cc +0.5 v v il input low voltage 4.5 v < v cc < 5.5 v ?0.5 0.8 v v ih1 reset high level input voltage (1) 0.8v cc v cc +0.5 v v il1 reset low level input voltage (1) ?0.5 0.2v cc ?0.1 v v hys reset pin hysteresis 0.3 v v lko v cc (min) for flash erase and program 2.5 4.2 v v ol output low voltage i ol = 20 a, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma, v cc = 4.5 v 0.25 0.45 v v oh output high voltage i oh = ?20 a, v cc = 4.5 v 4.4 4.49 v i oh = ?2 ma, v cc = 4.5 v 2.4 3.9 v i sb standby supply current for power-down mode csi >v cc ?0.3 v (2)(3) 100 200 a i li input leakage current v ss < v in < v cc ?1 0.1 1 a i lo output leakage current 0.45 v < v out < v cc ?10 5 10 a obsolete product(s) - obsolete product(s)
dc and ac parameters psd4135g2, psd4135g2v 88/104 doc id 7838 rev 2 i cc (dc) (4) operating supply current pld only pld_turbo = off, f = 0 mhz (note 5 ) 0 a/pt pld_turbo = on, f = 0 mhz 400 700 a/pt flash memory during flash memory write/erase only 15 30 ma read only, f = 0 mhz 0 0 ma sram f = 0 mhz 0 0 ma i cc (ac) pld ac adder (5) flash memory ac adder 2.5 3.5 ma/ mhz sram ac adder 1.5 3.0 ma/ mhz 1. reset (reset ) has hysteresis. v il1 is valid at or below 0.2v cc ?0.1. v ih1 is valid at or above 0.8v cc . 2. csi deselected or internal power-down mode is active. 3. pld is in non-turbo mode, and none of the inputs are switching. 4. i o =0 ma 5. please see figure 30 for the pld current calculation. table 52. dc characteristics 5 v (continued) symbol parameter test condition (in addition to those in table 47 ) min. typ. max. unit table 53. dc characteristics (3 v) symbol parameter test condition (in addition to those in table 47 ) min. typ. max. unit v ih input high voltage 3.0 v < v cc < 3.6 v 0.7v cc v cc +0.5 v v il input low voltage 3.0 v < v cc < 3.6 v ?0.5 0.8 v v ih1 reset high level input voltage (1) 0.8v cc v cc +0.5 v v il1 reset low level input voltage (1) ?0.5 0.2v cc ?0.1 v v hys reset pin hysteresis 0.3 v v lko v cc (min) for flash erase and program 1.5 2.3 v v ol output low voltage i ol = 20 a, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma, v cc = 4.5 v 0.15 0.45 v v oh output high voltage i oh = ?20 a, v cc = 4.5 v 2.9 2.99 v i oh = ?2 ma, v cc = 4.5 v 2.7 2.8 v i sb standby supply current for power-down mode csi >v cc ?0.3 v (2)(3) 50 100 a obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v dc and ac parameters doc id 7838 rev 2 89/104 i li input leakage current v ss < v in < v cc ?1 0.1 1 a i lo output leakage current 0.45 < v out < v cc ?10 5 10 a i cc (dc) (4) operating supply current pld only pld_turbo = off, f = 0 mhz (note 5 ) 0 a/pt pld_turbo = on, f = 0 mhz 200 400 a/pt flash memory during flash memory write/erase only 10 25 ma read only, f = 0 mhz 0 0 ma sram f = 0 mhz 0 0 ma i cc (ac) pld ac adder (5) flash memory ac adder 1.5 2.0 ma/ mhz sram ac adder 0.8 1.5 ma/ mhz 1. reset (reset ) has hysteresis. v il1 is valid at or below 0.2v cc ?0.1. v ih1 is valid at or above 0.8v cc . 2. csi deselected or internal power-down mode is active. 3. pld is in non-turbo mode, and none of the inputs are switching. 4. i o =0 ma 5. please see figure 30 for the pld current calculation. table 53. dc characteristics (3 v) (continued) symbol parameter test condition (in addition to those in table 47 ) min. typ. max. unit obsolete product(s) - obsolete product(s)
dc and ac parameters psd4135g2, psd4135g2v 90/104 doc id 7838 rev 2 figure 35. read timing 1. t avlx and t lxax are not required for 80c251 in page mode or 80c51xa in burst mode. t avlx t lxax 1 t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out ale /as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) e r/w ai02895 table 54. read timing (5 v) symbol parameter conditions -70 -90 turbo off unit min max min max t lv l x ale or as pulse width 15 20 ns t avlx address setup time (1) 46 ns t lxax address hold time 7 8 ns t avqv address valid to data valid 70 90 + 12 ns t slqv cs valid to data valid 75 100 ns t rlqv rd to data valid 8-bit bus (2) 24 32 ns rd or psen to data valid 8-bit bus, 8031, 80251 (3) 31 38 ns t rhqx rd data hold time (4) 00 ns t rlrh rd pulse width 27 32 ns t rhqz rd to data high-z 20 25 ns t ehel e pulse width 27 32 ns t theh r/w setup time to enable 6 10 ns obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v dc and ac parameters doc id 7838 rev 2 91/104 t eltl r/w hold time after enable 0 0 ns t avpv address input valid to address output delay (5) 20 25 ns 1. any input used to select an internal psd function. 2. rd timing has the same timing as ds , lds , and uds signals. 3. rd and psen have the same timing. 4. rd timing has the same timing as ds , lds , uds , and psen signals. 5. in multiplexed mode, latched addresses generated from adio delay to address output on any port. table 54. read timing (5 v) (continued) symbol parameter conditions -70 -90 turbo off unit min max min max table 55. read timing (3 v) symbol parameter conditions -90 -12 turbo off unit min max min max t lv l x ale or as pulse width 22 24 ns t avlx address setup time (1) 79 ns t lxax address hold time 8 10 ns t avqv address valid to data valid 90 120 + 20 ns t slqv cs valid to data valid 90 120 ns t rlqv rd to data valid 8-bit bus (2) 35 35 ns rd or psen to data valid 8-bit bus, 8031, 80251 (3) 45 48 ns t rhqx rd data hold time (4) 00 ns t rlrh rd pulse width 36 40 ns t rhqz rd to data high-z 38 40 ns t ehel e pulse width 38 42 ns t theh r/w setup time to enable 10 16 ns t eltl r/w hold time after enable 0 0 ns t avpv address input valid to address output delay (5) 30 35 ns 1. any input used to select an internal psd function. 2. rd timing has the same timing as ds , lds , and uds signals. 3. rd and psen have the same timing. 4. rd timing has the same timing as ds , lds , uds , and psen signals. 5. in multiplexed mode, latched addresses generated from adio delay to address output on any port. obsolete product(s) - obsolete product(s)
dc and ac parameters psd4135g2, psd4135g2v 92/104 doc id 7838 rev 2 figure 36. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlmv t wlwh t dvwh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale/as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi wr (ds) e r/ w ai02896 table 56. write timing (5 v) symbol parameter conditions -70 -90 unit min max min max t lv l x ale or as pulse width 15 20 ns t avlx address setup time (1) 46ns t lxax address hold time (1) 78ns t avwl address valid to leading edge of wr (1)(2) 815ns t slwl cs valid to leading edge of wr (2) 12 15 ns t dvwh wr data setup time (2) 25 35 ns t whdx wr data hold time (2)(3) 45ns t wlwh wr pulse width (2) 28 35 ns t whax1 trailing edge of wr to address invalid (2) 68ns t whax2 trailing edge of wr to dpld address invalid (2)(4) 00ns obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v dc and ac parameters doc id 7838 rev 2 93/104 t whpv trailing edge of wr to port output valid using i/o port data register (2) 27 30 ns t dvmv data valid to port output valid using macrocell register preset/clear (2)(5) 42 55 ns t avpv address input valid to address output delay (6) 20 25 ns t wlmv wr valid to port output valid using macrocell register preset/clear (2)(7) 48 55 ns 1. any input used to select an internal psd function. 2. wr has the same timing as e, ds , lds , uds , wrl , and wrh signals. 3. twhax is 6 ns when writing to the ou tput macrocell registers ab and bc. 4. twhax2 is the address hold time for dpld inputs that are used to generate sector select signals for internal psd memory. 5. assuming write is active before data becomes valid. 6. in multiplexed mode, latched address generated fr om adio delay to address output on any port. 7. assuming data is stable before active write signal. table 56. write timing (5 v) (continued) symbol parameter conditions -70 -90 unit min max min max table 57. write timing (3 v) symbol parameter conditions -90 -12 unit min max min max t lv l x ale or as pulse width 22 24 ns t avlx address setup time (1) 79ns t lxax address hold time (1) 810ns t avwl address valid to leading edge of wr (1)(2) 15 18 ns t slwl cs valid to leading edge of wr (2) 15 18 ns t dvwh wr data setup time (2) 40 45 ns t whdx wr data hold time (2)(3) 58ns t wlwh wr pulse width (2) 40 45 ns t whax1 trailing edge of wr to address invalid (2) 810ns t whax2 trailing edge of wr to dpld address invalid (2)(4) 00ns t whpv trailing edge of wr to port output valid using i/o port data register (2) 33 33 ns t dvmv data valid to port output valid using macrocell register preset/clear (2)(5) 65 68 ns obsolete product(s) - obsolete product(s)
dc and ac parameters psd4135g2, psd4135g2v 94/104 doc id 7838 rev 2 figure 37. input to output disable/enable t avpv address input valid to address output delay (6) 30 35 ns t wlmv wr valid to port output valid using macrocell register preset/clear (2)(7) 65 70 ns 1. any input used to select an internal psd function. 2. wr has the same timing as e, ds , lds , uds , wrl , and wrh signals. 3. twhax is 6 ns when writing to the ou tput macrocell registers ab and bc. 4. twhax2 is the address hold time for dpld inputs that are used to generate sector select signals for internal psd memory. 5. assuming write is active before data becomes valid. 6. in multiplexed mode, latched address generated fr om adio delay to address output on any port. 7. assuming data is stable be fore active write signal. table 57. write timing (3 v) (continued) symbol parameter conditions -90 -12 unit min max min max ter tea input input to output enable/disable ai02863 table 58. pld combinatorial timing (5 v) symbol parameter conditions -70 -90 fast pt aloc turbo off slew rate (1) unit min max min max t pd pld input pin/feedback to pld combinatorial output 20 25 + 2 + 12 ? 2 ns t ard pld array delay any macrocell 11 16 + 2 ns 1. fast slew rate output available on port c and port f. table 59. pld combinatorial timing (3 v) symbol parameter conditions -90 -12 fast pt aloc turbo off slew rate (1) unit min max min max t pd pld input pin/feedback to pld combinatorial output 38 43 + 4 + 20 ? 6 ns t ard pld array delay any macrocell 23 27 + 4 ns obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v dc and ac parameters doc id 7838 rev 2 95/104 1. fast slew rate output available on port c and port f. table 60. power-down timing (5 v) symbol parameter conditions -70 -90 unit min max min max t lv dv ale access time from power-down 80 90 ns t clwh maximum delay from apd enabled to internal pdn valid signal using clkin (pd1) 15 * t clcl (1) s 1. t clcl is the period of clkin (pd1). table 61. power-down timing (3 v) symbol parameter conditions -90 -12 unit min max min max t lv dv ale access time from power-down 128 135 ns t clwh maximum delay from apd enable to internal pdn valid signal using clkin (pd1) 15 * t clcl (1) s 1. t clcl is the period of clkin (pd1). obsolete product(s) - obsolete product(s)
dc and ac parameters psd4135g2, psd4135g2v 96/104 doc id 7838 rev 2 figure 38. reset (reset ) timing t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset table 62. reset (reset ) timing (5 v) symbol parameter conditions min max unit t nlnh reset active low time (1) 150 ns t nlnh?po power-on reset active low time 1 ms t nlnh?a warm reset (2) 25 s t opr reset high to operational device 120 ns 1. reset (reset ) does not reset flash memory program or erase cycles. 2. warm reset aborts flash memory program or erase cycles, and puts the device in read mode. table 63. reset (reset ) timing (3 v) symbol parameter conditions min max unit t nlnh reset active low time (1) 300 ns t nlnh?po power-on reset active low time 1 ms t nlnh?a warm reset (2) 25 s t opr reset high to operational device 300 ns 1. reset (reset ) does not reset flash memory program or erase cycles. 2. warm reset aborts flash memory program or erase cycles, and puts the device in read mode. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v dc and ac parameters doc id 7838 rev 2 97/104 table 64. program, write and erase timings (5 v) symbol parameter min. typ. max. unit flash program 8.5 s flash bulk erase (1) (pre-programmed) 3 30 s flash bulk erase (not pre-programmed) 10 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed) 2.2 s t whqv1 byte program 14 1200 s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase timeout 100 s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) (2)(3) 30 ns 1. programmed to all zero before erase. 2. the polling status, dq7, is valid tq7vqv time units before the data by te, dq0-dq7, is valid for reading. 3. dq7 is dq15 for motorola mcu with 16-bit data bus. table 65. program, write and erase times (3 v) symbol parameter min. typ. max. unit flash program 8.5 s flash bulk erase (1) (pre-programmed) 3 30 s flash bulk erase (not pre-programmed) 10 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed) 2.2 s t whqv1 byte program 14 1200 s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase timeout 100 s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) (2)(3) 30 ns 1. programmed to all zero before erase. 2. the polling status, dq7, is valid tq7vqv time units before the data by te, dq0-dq7, is valid for reading. 3. dq7 is dq15 for motorola mcu with 16-bit data bus. obsolete product(s) - obsolete product(s)
dc and ac parameters psd4135g2, psd4135g2v 98/104 doc id 7838 rev 2 figure 39. isc timing iscch tck tdi/tms isc outputs/tdo isc outputs/tdo t isccl t iscph t iscpsu t iscpvz t iscpzv t iscpco t ai02865 table 66. isc timing (5 v) symbol parameter conditions -70 -90 unit min max min max t isccf clock (tck, pc1) frequency (except for pld) (1) 20 18 mhz t iscch clock (tck, pc1) high time (except for pld) 23 26 ns t isccl clock (tck, pc1) low time (except for pld) 23 26 ns t isccfp clock (tck, pc1) frequency (pld only) (2) 22mhz t iscchp clock (tck, pc1) high time (pld only) 240 240 ns t iscclp clock (tck, pc1) low time (pld only) 240 240 ns t iscpsu isc port setup time 6 8 ns t iscph isc port hold time 5 5 ns t iscpco isc port clock to output 21 23 ns t iscpzv isc port high-impedance to valid output 21 23 ns t iscpvz isc port valid output to high-impedance 21 23 ns 1. for non-pld programming, erase or in isc by-pass mode. 2. for program or erase pld only. obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v package mechanical doc id 7838 rev 2 99/104 16 package mechanical in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. obsolete product(s) - obsolete product(s)
package mechanical psd4135g2, psd4135g2v 100/104 doc id 7838 rev 2 figure 40. lqfp80 - 80-lead plastic thin, quad, flat package outline 1. drawing is not to scale. table 67. lqfp80 - 80-lead plastic thin, quad, flat package mechanical data (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. symb mm inches typ min max typ min max a ? ? 1.600 ? ? 0.0630 a1 ? 0.050 0.150 ? 0.0020 0.0060 a2 1.400 1.350 1.450 0.0550 0.0530 0.0570 b 0.220 0.170 0.270 0.0090 0.0070 0.0110 c ? 0.090 0.200 ? 0.0040 0.0080 d 14.000 ? ? 0.5510 ? ? d1 12.000 ? ? 0.4720 ? ? d3 9.500 ? ? 0.3740 ? ? e 14.000 ? ? 0.5510 ? ? e1 12.000 ? ? 0.4720 ? ? e3 9.500 ? ? 0.3740 ? ? e 0.500 ? ? 0.0200 ? ? l 0.600 0.450 0.750 0.0240 0.0180 0.0300 l1 1.000 ? ? 0.0390 ? ? k073.507 ccc 0.080 ? ? 0.003 9x_me e1 ccc b e a2 a l a1 k d1 d e c d3 e3 l1 1 20 21 40 41 60 61 80 pin 1 identification obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v part numbering doc id 7838 rev 2 101/104 17 part numbering for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 68. ordering information scheme example: psd41 3 5 g 2 ? 90 u 1 t device type psd41 = flash psd for 16-bit mcus with simple psds sram size 3 = 64 kbit flash memory size 5 = 4 mbit i/o count g = 52 i/o 2nd non-volatile memory 2 = 256 kbit flash memory operating voltage blank = v cc = 4.5 to 5.5v v = v cc = 3.0 to 3.6v speed 70 = 70ns 90 = 90ns 12 = 120ns package u = ecopack lqfp80 temperature range blank = 0 to 70c (commercial) i = ?40 to 85c (industrial) option t = tape & reel packing obsolete product(s) - obsolete product(s)
pin assignments psd4135g2, psd4135g2v 102/104 doc id 7838 rev 2 appendix a pin assignments table 69. psd4235g2 lqfp80 pin no. pin assignments pin no. pin assignments pin no. pin assignments pin no. pin assignments 1 pd2 21 pg0 41 pc0 61 pb0 2 pd3 22 pg1 42 pc1 62 pb1 3 ad0 23 pg2 43 pc2 63 pb2 4 ad1 24 pg3 44 pc3 64 pb3 5 ad2 25 pg4 45 pc4 65 pb4 6 ad3 26 pg5 46 pc5 66 pb5 7 ad4 27 pg6 47 pc6 67 pb6 8 gnd 28 pg7 48 pc7 68 pb7 9v cc 29 v cc 49 gnd 69 v cc 10 ad5 30 gnd 50 gnd 70 gnd 11 ad6 31 pf0 51 pa0 71 pe0 12 ad7 32 pf1 52 pa1 72 pe1 13 ad8 33 pf2 53 pa2 73 pe2 14 ad9 34 pf3 54 pa3 74 pe3 15 ad10 35 pf4 55 pa4 75 pe4 16 ad11 36 pf5 56 pa5 76 pe5 17 ad12 37 pf6 57 pa6 77 pe6 18 ad13 38 pf7 58 pa7 78 pe7 19 ad14 39 reset 59 cntl0 79 pd0 20 ad15 40 cntl2 60 cntl1 80 pd1 obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v revision history doc id 7838 rev 2 103/104 18 revision history table 70. document revision history date revision changes 01-may-2000 1 document written in the wsi format. initial release 31-jan-2002 1.1 psd4135g2: flash in-system-programmable peripherals for 16-bit mcus: front page, and back two pages, in st format, added to the pdf file any references to waferscale, wsi, easyflash and psdsoft 2000 updated to st, st, flash+psd and psdsoft express 05-may-2009 2 document reformatted and restruct ured for consistency with other psds datasheet. added ta b l e 1 : p i n n a m e s and figure 2: logic diagram . added 3 v supply voltage psd4135g2v. removed sram standby mode and backup battery feature. all products are delivered in ecopack-compliant packages. renamed tqfp80 lqfp80, and updated table 67: lqfp80 - 80- lead plastic thin, quad, flat package mechanical data . obsolete product(s) - obsolete product(s)
psd4135g2, psd4135g2v 104/104 doc id 7838 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com obsolete product(s) - obsolete product(s)

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